Datasheet

Description Mode Min. Typ Max Units
17 SS high to tri-state Slave 10 -
18 SS low to SCK Slave 2 • t
ck
- -
Note: In SPI Programming mode the minimum SCK high/low period is:
• 2 • t
CLCLCL
for f
CK
< 12 MHz
• 3 • t
CLCL
for f
CK
> 12 MHz
Figure 33-3. SPI Interface Timing Requirements (Master Mode)
MOSI
(Data Output)
SCK
(CPOL = 1)
MISO
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
6 1
2 2
34 5
8
7
Figure 33-4. SPI Interface Timing Requirements (Slave Mode)
MISO
(Data Output)
SCK
(CPOL = 1)
MOSI
(Data Input)
SCK
(CPOL = 0)
SS
MSB LSB
LSBMSB
...
...
10
11 11
1213 14
17
15
9
X
16
33.7 Two-Wire Serial Interface Characteristics
Table in this section describes the requirements for devices connected to the two-wire serial bus. The
two-wire serial interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 33-5.
ATmega48PA/88PA/168PA
Electrical Characteristics
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 392