Datasheet

Figure 32-6. Serial Programming and Verify, V
CC
= 1.8 - 5.5V
VCC
GND
RESET
MOSI
MISO
SCK
XTAL1
PB5
PB6
PB7
+1.8 - 5.5V
AVCC
+1.8 - 5.5V
(2)
Note:
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin.
2. V
CC
- 0.3V < AVCC < V
CC
+ 0.3V, however, AVCC should always be within the specified voltage
range (V
CC
) for the device.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation
(in the Serial mode ONLY) and there is no need to first execute the chip erase instruction. The chip erase
operation turns the content of every memory location in both the program and EEPROM arrays into 0xFF.
Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods for the
serial clock (SCK) input are defined as follows:
• Low: > 2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
≥ 12 MHz
• High: > 2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
≥ 12 MHz
32.9.1 Serial Programming Pin Mapping
Table 32-16. Pin Mapping Serial Programming
Symbol Pins I/O Description
MOSI PB3 I Serial Data in
MISO PB4 O Serial Data out
SCK PB5 I Serial Clock
Note: The pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the
internal SPI interface.
ATmega48PA/88PA/168PA
Memory Programming (MEMPROG)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 379