Datasheet

Figure 32-1. Parallel Programming
VCC
GND
XTAL1
PD1
PD2
PD3
PD4
PD5
PD6
PC[1:0]:PB[5:0]
DATA
RESET
PD7
+12V
BS1
XA0
XA1
OE
RDY/BSY
PAGEL
PC2
WR
BS2
AVCC
+4.5 - 5.5V
+4.5 - 5.5V
Note: V
CC
- 0.3V < AV
CC
< V
CC
+ 0.3V; however, AV
CC
should always be within 4.5 - 5.5V
Table 32-12. Pin Name Mapping
Signal Name in
Programming Mode
Pin Name I/O Function
RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for
new command
OE PD2 I Output Enable (Active low)
WR PD3 I Write Pulse (Active low)
BS1 PD4 I Byte Select 1 (“0” selects Low byte, “1” selects High
byte)
XA0 PD5 I XTAL Action Bit 0
XA1 PD6 I XTAL Action Bit 1
PAGEL PD7 I Program memory and EEPROM Data Page Load
BS2 PC2 I Byte Select 2 (“0” selects Low byte, “1” selects 2’nd
High byte)
DATA {PC[1:0]: PB[5:0]} I/O Bi-directional Data bus (Output when OE is low)
Table 32-13. Pin Values Used to Enter Programming Mode
Pin Symbol Value
PAGEL Prog_enable[3] 0
XA1 Prog_enable[2] 0
ATmega48PA/88PA/168PA
Memory Programming (MEMPROG)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 370