Datasheet

the Z-pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit

set, or if no SPM instruction is executed within four clock cycles.

An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR register

(SPMCSR.BLBSET and SPMCSR.SPMEN), will read either the Lock bits or the Fuse bits (depending on

Z0 in the Z-pointer) into the destination register. Refer to Reading the Fuse and Lock Bits from Software

in this chapter.

Bit 2 – PGWRT Page Write

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles

executes page write, with the data stored in the temporary buffer. The page address is taken from the

high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon

completion of a page write, or if no SPM instruction is executed within four clock cycles. The CPU is

halted during the entire page write operation if the NRWW section is addressed.

Bit 1 – PGERS Page Erase

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles

executes page erase. The page address is taken from the high part of the Z-pointer. The data in R1 and

R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction

is executed within four clock cycles. The CPU is halted during the entire page write operation if the

NRWW section is addressed.

Bit 0 – SPMEN Store Program Memory

This bit enables the SPM instruction for the next four clock cycles. If written to one together with either

RWWSRE, BLBSET, PGWRT, or PGERS, the following SPM instruction will have a special meaning (see

the description above). If only SPMEN is written, the following SPM instruction will store the value in

R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The

SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed

within four clock cycles. During page erase and page write, the SPMEN bit remains high until the

operation is completed.

Writing any other combination than “0x10001”, “0x01001”, “0x00101”, “0x00011” or “0x00001” in the lower

five bits will have no effect.

ATmega48PA/88PA/168PA

Boot Loader Support – Read-While-Write Self-...

Datasheet Complete

DS40002011A-page 363