Datasheet

31.9.1 Store Program Memory Control and Status Register (SPMCSR)
Name: SPMCSR
Offset: 0x57 [ID-000004d0]
Reset: 0x00
Property: When addressing as I/O register: address offset is 0x37
The Store Program Memory Control and Status Register (SPMCSR) contains the control bits needed to
control the boot loader operations.
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Bit 7 6 5 4 3 2 1 0
SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 – SPMIE SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status register is set (one), the SPM ready
interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the
SPMCSR register is cleared.
Bit 6 – RWWSB Read-While-Write Section Busy
When a self-programming (page erase or page write) operation to the RWW section is initiated, the
RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be
accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming
operation is completed. Alternatively, the RWWSB bit will automatically be cleared if a page load
operation is initiated.
Bit 5 – SIGRD Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles
will read a byte from the signature row into the destination register. Refer to Reading the Fuse and Lock
Bits from Software in this chapter. An SPM instruction within four cycles after SIGRD and SPMEN are set
will have no effect. This operation is reserved for future use and should not be used.
Bit 4 – RWWSRE Read-While-Write Section Read Enable
When programming (page erase or page write) to the RWW section, the RWW section is blocked for
reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must
wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to
one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW
section. The RWW section cannot be re-enabled while the Flash is busy with a page erase or a page
write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load
operation will abort and the data loaded will be lost.
Bit 3 – BLBSET Boot Lock Bit Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles
sets Boot Lock bits and Memory Lock bits, according to the data in R0. The data in R1 and the address in
ATmega48PA/88PA/168PA
Boot Loader Support – Read-While-Write Self-...
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Datasheet Complete
DS40002011A-page 362