Datasheet

30.3.1 Store Program Memory Control and Status Register
Name: SPMCSR
Offset: 0x57 [ID-000004d0]
Reset: 0x00
Property: When addressing I/O registers as data space the offset address is 0x37
The Store Program Memory Control and Status register contains the control bits needed to control the
program memory operations.
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Bit 7 6 5 4 3 2 1 0
SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN
Access
R/W R R R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 – SPMIE SPM Interrupt Enable
When the SPMIE bit is written to '1', and the I-bit in the Status register is set ('1'), the SPM ready interrupt
will be enabled. The SPM ready interrupt will be executed as long as the SPMEN bit in the SPMCSR
register is cleared (SPMCSR.SPMEN). The interrupt will not be generated during EEPROM write or SPM.
Bit 6 – RWWSB Read-While-Write Section Busy
This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero.
Bit 5 – SIGRD Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles
will read a byte from the signature row into the destination register. Refer to Reading the Signature Row
from Software. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect.
This operation is reserved for future use and should not be used.
Bit 4 – RWWSRE Read-While-Write Section Read Enable
The functionality of this bit in ATmega48PA is a subset of the functionality in ATmega88PA and
ATmega168PA. If the RWWSRE bit is written while filling the temporary page buffer, the temporary page
buffer will be cleared and the data will be lost.
Bit 3 – BLBSET Boot Lock Bit Set
The functionality of this bit in ATmega48PA is a subset of the functionality in ATmega88PA and
ATmega168PA. An LPM instruction within three cycles after BLBSET and SPMEN are set in the
SPMCSR register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into
the destination register. Refer to 30.2.2 Reading the Fuse and Lock Bits from Software
Bit 2 – PGWRT Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles
executes page write, with the data stored in the temporary buffer. The page address is taken from the
high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon
completion of a page write, or if no SPM instruction is executed within four clock cycles. The CPU is
halted during the entire page write operation.
ATmega48PA/88PA/168PA
Self-Programming the Flash
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 344