Datasheet

28.9.4 ADC Data Register Low and High Byte (ADLAR=1)

Name: ADCL and ADCH (ADLAR = 1)

Offset: 0x78

Reset: 0x00

The ADCL and ADCH register pair represents the 16-bit value, ADC data register. The low byte [7:0]

(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset

+ 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter

Registers.

When an ADC conversion is complete, the result is found in these two registers.

When ADCL is read, the ADC data register is not updated until ADCH is read. Consequently, if the result

is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise,

ADCL must be read first, then ADCH.

The ADLAR bit and the MUXn bits in ADMUX affect the way the result is read from the registers. If

ADLAR is set (ADLAR=1), the result is left adjusted. If ADLAR is cleared (ADLAR=0, which is the default

value), the result is right adjusted.

Bit 15 14 13 12 11 10 9 8

ADC[9:2]

Access

R R R R R R R R

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

ADC[1:0]

Access

R R

Reset 0 0

Bits 15:6 – ADC[9:0] ADC Conversion Result

These bits represent the result from the conversion. Refer to 28.7 ADC Conversion Result for details.