Datasheet

Figure 28-6. ADC Timing Diagram, Auto Triggered Conversion
1 2 3 4 5 6 7 8
9
10 11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
Trigger
Source
ADIF
ADCH
ADCL
Cycle Number
1 2
One Conversion Next Conversion
Conversion
Complete
Prescaler
Reset
ADATE
Prescaler
Reset
Sample &
Hold
MUX and REFS
Update
Figure 28-7. ADC Timing Diagram, Free Running Conversion
11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
1
2
One Conversion Next Conversion
3 4
Conversion
Complete
Sample and Hold
MUX and REFS
Update
Table 28-1. ADC Conversion Time
Condition Sample & Hold
[Cycles from Start of Conversion]
Conversion Time
[Cycles]
First conversion 13.5 25
Normal conversions, single ended 1.5 13
Auto Triggered conversions 2 13.5
28.5 Changing Channel or Reference Selection
The analog channel selection bits (MUX) and the Reference Selection bits (REFS) bits in the ADC
Multiplexer Selection Register (ADMUX.MUX and ADMUX.REFS) are single buffered through a
temporary register to which the CPU has random access. This ensures that the channels and reference
ATmega48PA/88PA/168PA
Analog-to-Digital Converter (ADC)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 319