Datasheet

11.3.1 Status Register

Name: SREG

Offset: 0x5F

Reset: 0x00

Property: When addressing as I/O Register: address offset is 0x3F

When addressing I/O registers as data space using LD and ST instructions, the provided offset must be

used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an

I/O address offset within 0x00 - 0x3F.

Bit 7 6 5 4 3 2 1 0

I T H S V N Z C

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 – I Global Interrupt Enable

The global interrupt enable bit must be set for the interrupts to be enabled. The individual interrupt enable

control is then performed in separate control registers. If the Global Interrupt Enable register is cleared,

none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is

cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable

subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI

instructions, as described in the instruction set reference.

Bit 6 – T Copy Storage

The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for

the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a

bit in T can be copied into a bit in a register in the register file by the BLD instruction.

Bit 5 – H Half Carry Flag

The half carry flag H indicates a half carry in some arithmetic operations. Half carry flag is useful in BCD

arithmetic. See the Instruction Set Description for detailed information.

Bit 4 – S Sign Flag, S = N ㊉ V

The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag

V. See the Instruction Set Description for detailed information.

Bit 3 – V Two’s Complement Overflow Flag

The two’s complement overflow flag V supports two’s complement arithmetic. See the Instruction Set

Description for detailed information.

Bit 2 – N Negative Flag

The negative flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set

Description for detailed information.

Bit 1 – Z Zero Flag

The zero flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set

Description for detailed information.

ATmega48PA/88PA/168PA

AVR CPU Core

Datasheet Complete

DS40002011A-page 31