Datasheet

Figure 26-16. Formats and States in the Slave Transmitter Mode
S SLA R A A
0xA8 0xB8
A
0xB0
n
P or S
0xC0
DATA A
A
0xC8
P or SAll 1's
A
Reception of the own
slave address and one or
more data bytes
Arbitration lost as master
and addressed as slave
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
From master to slave
From slave to master
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Ser ial Bus. The
prescaler bits are zero or masked to zero.
DATA
DATA
26.7.4 Slave Receiver Mode
In the Slave Receiver (SR) mode, a number of data bytes are received from a master transmitter (see
figure below). All the status codes mentioned in this section assume that the prescaler bits are zero or are
masked to zero.
Figure 26-17. Data transfer in Slave Receiver mode
Device 3
Device n
SDA
SCL
........
R1 R2
V
CC
Device 2
MASTER
TRANSMITTER
Device 1
SLAVE
RECEIVER
To initiate the SR mode, the TWI (Slave) Address Register n (TWARn) and the TWI Control Register n
(TWCRn) must be initialized as follows:
The upper seven bits of TWARn are the address to which the two-wire serial interface will respond when
addressed by a master (TWARn.TWA[6:0]). If the LSB of TWARn is written to TWARn.TWGCI=1, the TWI
n will respond to the general call address (0x00), otherwise, it will ignore the general call address.
ATmega48PA/88PA/168PA
Two-Wire Serial Interface (TWI)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 294