Datasheet

address pointer for lookup tables in Flash program memory. These added function registers are the 16-bit

X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a

Status register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly

address the whole address space. Most AVR instructions have a single 16-bit word format. Every

program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided into two sections, the Boot Program section and the Application

Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM

instruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.

The Stack is effectively allocated in the general data SRAM, and consequently, the Stack size is only

limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the Stack

Pointer (SP) in the Reset routine (before subroutines or interrupts are executed). The SP is read/write

accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing

modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt

enable bit in the Status register. All interrupts have a separate interrupt vector in the interrupt vector table.

The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt

vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control registers, SPI, and

other I/O functions. The I/O memory can be accessed directly, or as the data space locations following

those of the register file, 0x20 - 0x5F. In addition, this device has extended I/O space from 0x60 - 0xFF in

SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

11.2 Arithmetic Logic Unit (ALU)

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working

registers. Within a single clock cycle, arithmetic operations between general purpose registers or

between a register and an immediate are executed. The ALU operations are divided into three main

categories: arithmetic, logical, and bit-functions. Some implementations of the architecture provide a

powerful multiplier supporting both signed/unsigned multiplication and fractional format. See Instruction

Set Summary section for a detailed description.