Datasheet

26.5.2 Bit Rate Generator Unit
This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by
settings in the TWI Bit Rate Register (TWBRn) and the Prescaler bits in the TWI Status Register
(TWSRn). Slave operation does not depend on bit rate or prescaler settings, but the CPU clock frequency
in the slave must be at least 16 times higher than the SCL frequency. Note that slaves may prolong the
SCL low period, thereby reducing the average TWI bus clock period.
The SCL frequency is generated according to the following equation:
SCLfrequency =
CPUClockfrequency
16 + 2(TWBR) 
PrescalerValue
• TWBR = Value of the TWI Bit Rate Register TWBRn
• PrescalerValue = Value of the prescaler, see description of the TWI Prescaler bits in the TWSR
Status Register description (TWSRn.TWPS[1:0])
Note: Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus
line load. See the Two-Wire Serial Interface Characteristics for a suitable value of the pull-up resistor.
Related Links
33.7 Two-Wire Serial Interface Characteristics
26.5.3 Bus Interface Unit
This unit contains the Data and Address Shift Register (TWDRn), a START/STOP controller, and
arbitration detection hardware. The TWDRn contains the address or data bytes to be transmitted, or the
address or data bytes received. In addition to the 8-bit TWDRn, the bus interface unit also contains a
register containing the (N)ACK bit to be transmitted or received. This (N)ACK register is not directly
accessible by the application software. However, when receiving, it can be set or cleared by manipulating
the TWI Control Register (TWCRn). When in Transmitter mode, the value of the received (N)ACK bit can
be determined by the value in the TWSRn.
The START/STOP controller is responsible for generation and detection of START, REPEATED START,
and STOP conditions. The START/STOP controller is able to detect the START and STOP conditions
even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up if addressed by a
master.
If the TWI has initiated a transmission as master, the arbitration detection hardware continuously monitors
the transmission trying to determine if arbitration is in process. If the TWI has lost an arbitration, the
control unit is informed. Correct action can then be taken and appropriate status codes generated.
26.5.4 Address Match Unit
The address match unit checks if received address bytes match the seven-bit address in the TWI
Address Register (TWARn). If the TWI General Call Recognition Enable bit (TWARn.TWGCE) is written
to '1', all incoming address bits will also be compared against the general call address. Upon an address
match, the control unit is informed, allowing the correct action to be taken. The TWI may or may not
acknowledge its address, depending on settings in the TWI Control Register (TWCRn). The address
match unit is able to compare addresses even when the AVR MCU is in Sleep mode, enabling the MCU
to wake up if addressed by a master.
26.5.5 Control Unit
The control unit monitors the TWI bus and generates responses corresponding to settings in the TWI
Control Register (TWCRn). When an event requiring the attention of the application occurs on the TWI
bus, the TWI Interrupt flag (TWINT) is asserted. In the next clock cycle, the TWI Status Register (TWSRn)
ATmega48PA/88PA/168PA
Two-Wire Serial Interface (TWI)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 278