Datasheet

Figure 26-7. SCL Synchronization Between Multiple Masters
TA
low
TA
high
SCL from
Master A
SCL from
Master B
SCL Bus
Line
TB
low
TB
high
Masters Start
Counting Low Period
Masters Start
Counting High Period
Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the
value read from the SDA line does not match the value the master had output, it has lost the arbitration.
Note that a master can only lose arbitration when it outputs a high SDA value while another master
outputs a low value. The losing master should immediately go to Slave mode, checking if it is being
addressed by the winning master. The SDA line should be left high, but losing masters are allowed to
generate a clock signal until the end of the current data or address packet. Arbitration will continue until
only one master remains, and this may take many bits. If several masters are trying to address the same
slave, arbitration will continue into the data packet.
Figure 26-8. Arbitration Between Two Masters
SDA from
Master A
SDA from
Master B
SDA Line
Synchronized
SCL Line
START
Master A Loses
Arbitration, SDA
A
SDA
Note that arbitration is not allowed between:
• A REPEATED START condition and a data bit
• A STOP condition and a data bit
• A REPEATED START and a STOP condition
ATmega48PA/88PA/168PA
Two-Wire Serial Interface (TWI)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 276