Datasheet

Table 24-10. Stop Bit Settings
USBS0 Stop Bit(s)
0 1-bit
1 2-bit
This bit is reserved in Master SPI Mode (MSPIM).
Bit 2 – UCSZ01 / UDORD0 USART Character Size / Data Order
UCSZ0[1:0]: USART Modes: The UCSZ0[1:0] bits combined with the UCSZ02 bit in UCSR0B sets the
number of data bits (Character Size) in a frame the receiver and transmitter use.
Table 24-11. Character Size Settings
UCSZ0[2:0] Character Size
000 5-bit
001 6-bit
010 7-bit
011 8-bit
100 Reserved
101 Reserved
110 Reserved
111 9-bit
UDPRD0: Master SPI Mode: When set to one the LSB of the data word is transmitted first. When set to
zero the MSB of the data word is transmitted first. Refer to the USART in SPI Mode - Frame Formats for
details.
Bit 1 – UCSZ00 / UCPHA0 USART Character Size / Clock Phase
UCSZ00: USART Modes: Refer to UCSZ01.
UCPHA0: Master SPI Mode: The UCPHA0 bit setting determine if data is sampled on the leasing edge
(first) or tailing (last) edge of XCK0. Refer to the SPI Data Modes and Timing for details.
Bit 0 – UCPOL0 Clock Polarity 0
USART0 Modes: This bit is used for synchronous mode only. Write this bit to zero when Asynchronous
mode is used. The UCPOL0 bit sets the relationship between data output change and data input sample,
and the Synchronous Clock (XCK0).
Table 24-12. USART Clock Polarity Settings
UCPOL0 Transmitted Data Changed (Output of TxD0
Pin)
Received Data Sampled (Input on RxD0
Pin)
0 Rising XCK0 Edge Falling XCK0 Edge
1 Falling XCK0 Edge Rising XCK0 Edge
ATmega48PA/88PA/168PA
Universal Synchronous Asynchronous Receiver ...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 262