Datasheet

24.12.4 USART Control and Status Register 0 C
Name: UCSR0C
Offset: 0xC2
Reset: 0x06
Property: -
Bit 7 6 5 4 3 2 1 0
UMSEL0 [1:0] UPM0 [1:0] USBS0 UCSZ01 /
UDORD0
UCSZ00 /
UCPHA0
UCPOL0
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 1 1 0
Bits 7:6 – UMSEL0 [1:0] USART Mode Select 0
These bits select the mode of operation of the USART0
Table 24-8. USART Mode Selection
UMSEL0[1:0] Mode
00 Asynchronous USART
01 Synchronous USART
10 Reserved
11 Master SPI (MSPIM)
(1)
Note:
1. The UDORD0, UCPHA0, and UCPOL0 can be set in the same write operation where the MSPIM is
enabled.
Bits 5:4 – UPM0 [1:0] USART Parity Mode 0
These bits enable and set type of parity generation and check. If enabled, the transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The receiver
will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is
detected, the UPE0 Flag in UCSR0A will be set.
Table 24-9. USART Mode Selection
UPM0[1:0] ParityMode
00 Disabled
01 Reserved
10 Enabled, Even Parity
11 Enabled, Odd Parity
These bits are reserved in Master SPI Mode (MSPIM).
Bit 3 – USBS0 USART Stop Bit Select 0
This bit selects the number of stop bits to be inserted by the transmitter. The receiver ignores this setting.
ATmega48PA/88PA/168PA
Universal Synchronous Asynchronous Receiver ...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 261