Datasheet

24.12.2 USART Control and Status Register 0 A
Name: UCSR0A
Offset: 0xC0
Reset: 0x20
Property: -
Bit 7 6 5 4 3 2 1 0
RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0
Access
R R/W R R R R R/W R/W
Reset 0 0 1 0 0 0 0 0
Bit 7 – RXC0 USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is
empty (i.e., does not contain any unread data). If the receiver is disabled, the receive buffer will be
flushed and consequently the RXC0 bit will become zero. The RXC0 flag can be used to generate a
receive complete interrupt (see description of the RXCIE0 bit).
Bit 6 – TXC0 USART Transmit Complete
This flag bit is set when the entire frame in the transmit shift register has been shifted out and there are
no new data currently present in the transmit buffer (UDR0). The TXC0 flag bit is automatically cleared
when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.
The TXC0 flag can generate a transmit complete interrupt (see description of the TXCIE0 bit).
Bit 5 – UDRE0 USART Data Register Empty
The UDRE0 flag indicates if the transmit buffer (UDR0) is ready to receive new data. If UDRE0 is one, the
buffer is empty, and therefore ready to be written. The UDRE0 flag can generate a data register empty
interrupt (see description of the UDRIE0 bit). UDRE0 is set after a reset to indicate that the transmitter is
ready.
Bit 4 – FE0 Frame Error
This bit is set if the next character in the receive buffer had a frame error when received. I.e., when the
first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer
(UDR0) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero
when writing to UCSR0A.
This bit is reserved in Master SPI Mode (MSPIM).
Bit 3 – DOR0 Data OverRun
This bit is set if a data overrun condition is detected. A data overrun occurs when the receive buffer is full
(two characters), it is a new character waiting in the receive shift register, and a new start bit is detected.
This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to
UCSR0A.
This bit is reserved in Master SPI Mode (MSPIM).
Bit 2 – UPE0 USART Parity Error
This bit is set if the next character in the receive buffer had a parity error when received and the parity
checking was enabled at that point (UPM01 = 1). This bit is valid until the receive buffer (UDR0) is read.
Always set this bit to zero when writing to UCSR0A.
ATmega48PA/88PA/168PA
Universal Synchronous Asynchronous Receiver ...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 257