Datasheet

24.12.1 USART I/O Data Register 0

Name: UDR0

Offset: 0xC6

Reset: 0x00

Property: -

The USART transmit data buffer register and USART receive data buffer registers share the same I/O

address referred to as USART Data Register (UDR0). The Transmit Data Buffer register (TXB) will be the

destination for data written to the UDR0 location. Reading the UDR0 location will return the contents of

the Receive Data Buffer register (RXB).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the transmitter and set to zero by

the receiver.

The transmit buffer can only be written when the UDRE0 Flag in the UCSR0A register is set. Data written

to UDR0 when the UDRE0 flag is not set, will be ignored by the USART transmitter. When data is written

to the transmit buffer, and the transmitter is enabled, the transmitter will load the data into the Transmit

Shift register when the Shift register is empty. Then the data will be serially transmitted on the TxD0 pin.

The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive

buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-Write instructions

(SBI and CBI) on this location. Be careful when using bit test instructions (SBIC and SBIS), since these

also will change the state of the FIFO.

Bit 7 6 5 4 3 2 1 0

TXB / RXB[7:0]

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 7:0 – TXB / RXB[7:0] USART Transmit / Receive Data Buffer

ATmega48PA/88PA/168PA

Universal Synchronous Asynchronous Receiver ...

Datasheet Complete

DS40002011A-page 256