Datasheet

Figure 24-6. Sampling of Data and Parity Bit
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
BIT n
1 2 3 4 5 6 7 8 1
RxDn
Sample
(U2X = 0)
Sample
(U2X = 1)
The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to
the three samples in the center of the received bit: If two or all three center samples (those marked by
their sample number inside boxes) have high levels, the received bit is registered to be a logic '1'. If two
or all three samples have low levels, the received bit is registered to be a logic '0'. This majority voting
process acts as a low pass filter for the incoming signal on the RxDn pin. The recovery process is then
repeated until a complete frame is received, including the first stop bit. The receiver only uses the first
stop bit of a frame.
The following figure shows the sampling of the stop bit and the earliest possible beginning of the start bit
of the next frame.
Figure 24-7. Stop Bit Sampling and Next Start Bit Sampling
1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1
STOP 1
1 2 3 4 5 6 0/1
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
(A) (B) (C)
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is
registered to have a logic '0' value, the Frame Error (UCSRnA.FE) flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of the bits
used for majority voting. For Normal Speed mode, the first low level sample can be taken at the point
marked (A) in the figure above. For Double Speed mode, the first low level must be delayed to (B). (C)
marks a stop bit of full length. The early start bit detection influences the operational range of the receiver.
24.9.3 Asynchronous Operational Range
The operational range of the receiver is dependent on the mismatch between the received bit rate and
the internally generated baud rate. If the transmitter is sending frames at too fast or too slow bit rates or
the internally generated baud rate of the receiver does not have a similar base frequency (see
recommendations below), the receiver will not be able to synchronize the frames to the start bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal receiver
baud rate.

slow
=
 + 1 
  1 +    + 


fast
=
 + 2 
 + 1  + 

• D: Sum of character size and parity size (D = 5 to 10 bit).
• S: Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed mode.
ATmega48PA/88PA/168PA
Universal Synchronous Asynchronous Receiver ...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 250