Datasheet

conditions and protocol handling. The FE flag is not affected by the setting of the USBS bit in UCSRnC
since the receiver ignores all, except for the first, stop bits. For compatibility with future devices, always
set this bit to zero when writing to UCSRnA.
The DOR flag indicates data loss due to a receiver buffer full condition. A DOR occurs when the receive
buffer is full (two characters), a new character is waiting in the Receive Shift register, and a new start bit
is detected. If the DOR flag is set, one or more serial frames were lost between the last frame read from
UDR, and the next frame read from UDR. For compatibility with future devices, always write this bit to
zero when writing to UCSRnA. The DOR flag is cleared when the frame received was successfully moved
from the Shift register to the receive buffer.
The Parity Error (UPE) flag indicates that the next frame in the receive buffer had a UPE when received.
If Parity Check is not enabled the UPE bit will always read '0'. For compatibility with future devices,
always set this bit to zero when writing to UCSRnA. For more details see Parity Bit Calculation and 'Parity
Checker' below.
24.8.5 Parity Checker
The parity checker is active when the high USART Parity Mode bit 1 in the USART Control and Status
Register n C (UCSRnC.UPM[1]) is written to '1'. The type of parity check to be performed (odd or even) is
selected by the UCSRnC.UPM[0] bit. When enabled, the parity checker calculates the parity of the data
bits in incoming frames and compares the result with the Parity bit from the serial frame. The result of the
check is stored in the receive buffer together with the received data and stop bits. The USART parity error
flag in the USART Control and Status Register n A (UCSRnA.UPE) can then be read by software to
check if the frame had a parity error.
The UPEn bit is set if the next character that can be read from the receive buffer had a parity error when
received and the parity checking was enabled at that point (UPM[1] = 1). This bit is valid until the receive
buffer (UDRn) is read.
24.8.6 Disabling the Receiver
In contrast to the transmitter, disabling of the receiver will be immediate. Data from ongoing receptions
will, therefore, be lost. When disabled (i.e., UCSRnB.RXEN is written to zero) the receiver will no longer
override the normal function of the RxDn port pin. The receiver buffer FIFO will be flushed when the
receiver is disabled. Remaining data in the buffer will be lost.
24.8.7 Flushing the Receive Buffer
The receiver buffer FIFO will be flushed when the receiver is disabled, i.e., the buffer will be emptied of its
contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for
instance an error condition, read the UDRn I/O location until the RXCn flag is cleared.
The following code shows how to flush the receive buffer of USART0.
Assembly Code Example
USART_Flush:
in r16, UCSR0A
sbrs r16, RXC
ret
in r16, UDR0
rjmp USART_Flush
C Code Example
void USART_Flush( void )
{
ATmega48PA/88PA/168PA
Universal Synchronous Asynchronous Receiver ...
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Datasheet Complete
DS40002011A-page 248