Datasheet

Figure 24-2. Clock Generation Logic, Block Diagram
Prescaling
Down-Counter
/2
UBRRn
/4 /2
f
osc
UBRR
n
+1
Sync
Register
OSC
XCKn
Pin
txclk
U2Xn
UMSELn
DDR_XCKn
0
1
0
1
xcki
xcko
DDR_XCKn
rxclk
0
1
1
0
Edge
Detector
UCPOLn
Signal description:
• txclk: Transmitter clock (internal signal).
• rxclk: Receiver base clock (internal signal).
• xcki: Input from XCKn pin (internal signal). Used for synchronous slave operation.
• xcko: Clock output to XCKn pin (internal signal). Used for synchronous master operation.
• f
osc
: System clock frequency.
24.4.1 Internal Clock Generation – The Baud Rate Generator
Internal clock generation is used for the Asynchronous and the Synchronous Master modes of operation.
The description in this section refers to the clock generation logic block diagram in the previous section.
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock (f
osc
), is
loaded with the UBRRn value each time the counter has counted down to zero or when the UBRRnL
register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate
generator clock output (= f
osc
/(UBRRn+1)). The transmitter divides the baud rate generator clock output
by 2, 8, or 16 depending on the mode. The baud rate generator output is used directly by the receiver’s
clock and data recovery units. However, the recovery units use a state machine that uses 2, 8, or 16
states depending on the mode set by the state of the UMSEL, U2Xn and DDR_XCK bits.
The table below contains equations for calculating the baud rate (in bits per second) and for calculating
the UBRRn value for each mode of operation using an internally generated clock source.
Table 24-1. Equations for Calculating Baud Rate Register Setting
Operating Mode Equation for Calculating Baud
Rate(1)
Equation for Calculating UBRRn
Value
Asynchronous Normal mode
(U2Xn = 0)
BAUD =

OSC
16
 + 1
 =

OSC
16BAUD
 1
Asynchronous Double Speed
mode (U2Xn = 1)
BAUD =

OSC
8
 + 1
 =

OSC
8BAUD
 1
Synchronous Master mode
BAUD =

OSC
2
 + 1
 =

OSC
2BAUD
 1
ATmega48PA/88PA/168PA
Universal Synchronous Asynchronous Receiver ...
© 2018 Microchip Technology Inc.
Datasheet Complete
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