Datasheet

Figure 24-1. USART Block Diagram
PARITY
GENERATOR
UBRRn [H:L]
UDRn(Transmit)
UCSRnA UCSRnB UCSRnC
BAUD RATE GENERATOR
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER RxDn
TxDn
PIN
CONTROL
UDRn (Receive)
PIN
CONTROL
XCKn
DATA
RECOVERY
CLOCK
RECOVERY
PIN
CONTROL
TX
CONTROL
RX
CONTROL
PARITY
CHECKER
DATA BUS
OSC
SYNC LOGIC
Clock Generator
Transmitter
Receiver
Note: Refer to the Pin Configurations and the I/O-Ports description for USART pin placement.
24.4 Clock Generation
The clock generation logic generates the base clock for the transmitter and receiver. The USART
supports four modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master
synchronous, and Slave synchronous mode. The USART mode select bit 0 in the USART Control and
Status Register n C (UCSRnC.UMSELn0) selects between asynchronous and synchronous operation.
Double speed (asynchronous mode only) is controlled by the U2Xn found in the UCSRnA register. When
using synchronous mode (UMSELn0=1), the data direction register for the XCKn pin (DDR_XCKn)
controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is
only active when using Synchronous mode.
Below is a block diagram of the clock generation logic.
ATmega48PA/88PA/168PA
Universal Synchronous Asynchronous Receiver ...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 238