Datasheet

24. Universal Synchronous Asynchronous Receiver Transceiver (USART)
24.1 Features
• Full Duplex Operation (Independent Serial Receive and Transmit Registers)
• Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation
• High-Resolution Baud Rate Generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data OverRun Detection
• Framing Error Detection
• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
• Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete
• Multi-processor Communication Mode
• Double Speed Asynchronous Communication Mode
24.2 Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly
flexible serial communication device.
The USART can also be used in Master SPI mode. The Power Reduction USART bit in the Power
Reduction Register (PRR.PRUSARTn) must be written to '0' in order to enable USARTn.
Related Links
25. USART in SPI (USARTSPI) Mode
18. I/O-Ports
14.12.3 PRR
24.3 Block Diagram
In the USART block diagram, the CPU accessible I/O registers and I/O pins are shown in bold. The
dashed boxes in the block diagram separate the three main parts of the USART (listed from the top):
Clock generator, transmitter, and receiver. Control registers are shared by all units. The clock generation
logic consists of synchronization logic for external clock input used by synchronous slave operation, and
the baud rate generator. The XCKn (Transfer clock) pin is only used by synchronous transfer mode. The
transmitter consists of a single write buffer, a serial Shift register, parity generator, and control logic for
handling different serial frame formats. The write buffer allows a continuous transfer of data without any
delay between frames. The receiver is the most complex part of the USART module due to its clock and
data recovery units. The recovery units are used for asynchronous data reception. In addition to the
recovery units, the receiver includes a parity checker, control logic, a Shift register, and a two-level
receive buffer (UDRn). The receiver supports the same frame formats as the transmitter and can detect
frame error, data overrun, and parity errors.
ATmega48PA/88PA/168PA
Universal Synchronous Asynchronous Receiver ...
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Datasheet Complete
DS40002011A-page 237