Datasheet

23.5.2 SPI Status Register 0

Name: SPSR0

Offset: 0x4D [ID-000004d0]

Reset: 0x00

Property: When addressing as I/O Register: address offset is 0x2D

When addressing I/O registers as data space using LD and ST instructions, the provided offset must be

used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an

I/O address offset within 0x00 - 0x3F.

Bit 7 6 5 4 3 2 1 0

SPIF0 WCOL0 SPI2X0

Access

R R R/W

Reset 0 0 0

Bit 7 – SPIF0 SPI Interrupt Flag

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set

and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this

will also set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding interrupt

handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF

set, then accessing the SPI Data Register (SPDR).

Bit 6 – WCOL0 Write Collision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and

the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the

SPI Data Register.

Bit 0 – SPI2X0 Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in

Master mode (refer to Table 23-5). This means that the minimum SCK period will be two CPU clock

periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fosc/4 or lower.

The SPI interface is also used for program memory and EEPROM downloading or uploading. See Serial

Downloading for serial programming and verification.