Datasheet

22.11.1 TC2 Control Register A
Name: TCCR2A
Offset: 0xB0
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
COM2A[1:0] COM2B[1:0] WGM2[1:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 7:6 – COM2A[1:0] Compare Output Mode for Channel A
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A[1:0] bits are
set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However,
note that the Data Direction Register (DDR) bit corresponding to the OC2A pin must be set in order to
enable the output driver.
When OC2A is connected to the pin, the function of the COM2A[1:0] bits depends on the WGM2[2:0] bit
setting. The table below shows the COM2A[1:0] bit functionality when the WGM2[2:0] bits are set to a
normal or CTC mode (non-PWM).
Table 22-3. Compare Output Mode, Non-PWM
COM2A[1] COM2A[0] Description
0 0 Normal port operation, OC2A disconnected.
0 1 Toggle OC2A on compare match.
1 0 Clear OC2A on compare match.
1 1 Set OC2A on compare match .
The table below shows the COM2A[1:0] bit functionality when the WGM2[1:0] bits are set to fast PWM
mode.
Table 22-4. Compare Output Mode, Fast PWM
(1)
COM2A[1] COM2A[0] Description
0 0 Normal port operation, OC2A disconnected.
0 1 WGM2[2:0]: Normal port operation, OC2A disconnected
WGM2[2:1]: Toggle OC2A on compare match
1 0 Clear OC2A on compare match, set OC2A at BOTTOM (non-inverting mode)
1 1 Set OC2A on compare match, clear OC2A at BOTTOM (inverting mode)
Note:
1. A special case occurs when OCR2A equals TOP and COM2A[1] is set. In this case the compare
match is ignored, but the set or clear is done at BOTTOM. Refer to 22.7.3 Fast PWM Mode for
details.
ATmega48PA/88PA/168PA
8-bit Timer/Counter2 (TC2) with PWM and A...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 213