Datasheet

Figure 22-5. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A
Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
However, changing TOP to a value close to BOTTOM when the counter is running with none or a low
prescaler value must be done with care since the CTC mode does not have the double buffering feature.
If the new value written to OCR2A is lower than the current value of TCNT2, the counter will miss the
compare match. The counter will then have to count to its maximum value (0xFF) and wrap around
starting at 0x00 before the compare match can occur.
For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on
each compare match by setting the Compare Output mode bits to toggle mode (COM2A[1:0] = 1). The
OC2A value will not be visible on the port pin unless the data direction for the pin is set to output. The
waveform generated will have a maximum frequency of f
OC2A
= f
clk_I/O
/2 when OCR2A is set to zero
(0x00). The waveform frequency is defined by the following equation:

OCnx
=

clk_I/O
2   
1 + OCRnx
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter
counts from MAX to 0x00.
22.7.3 Fast PWM Mode
The fast Pulse-Width Modulation (fast PWM) mode (WGM2[2:0] = 0x3 or 0x7) provides a high frequency
PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope
operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as
0xFF when WGM2[2:0] = 0x3, and OCR2A when WGM2[2:0] = 0x7. In non-inverting Compare Output
mode, the Output Compare (OC2x) is cleared on the compare match between TCNT2 and OCR2x and
set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and cleared at
BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice
as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the
fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency
allows physically small sized external components (coils, capacitors), and therefore reduces total system
cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The
counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is
depicted in the following figure. The TCNT2 value is in the timing diagram shown as a histogram for
ATmega48PA/88PA/168PA
8-bit Timer/Counter2 (TC2) with PWM and A...
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Datasheet Complete
DS40002011A-page 206