Datasheet

The following figure shows a block diagram of the output compare unit.
Figure 22-3. Output Compare Unit, Block Diagram
OCFnx (Int.Req.)
=(8-bit Comparator )
OCRnx
OCnx
DATA BUS
TCNTn
WGMn[1:0]
Waveform Generator
top
FOCn
COMnx[1:0]
bottom
The OCR2x is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the
Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The
double buffering synchronizes the update of the OCR2x to either top or bottom of the counting sequence.
The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR2x access may seem complex, but this is not the case. When the double buffering is enabled,
the CPU has access to the OCR2x buffer register, and if double buffering is disabled the CPU will access
the OCR2x directly.
Related Links
19.7 Modes of Operation
22.5.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a
one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the OCF2x Flag or
reload/clear the timer, but the OC2x pin will be updated as if a real compare match had occurred (the
COM2x[1:0] bits settings define whether the OC2x pin is set, cleared or toggled).
22.5.2 Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 register will block any compare match that occurs in the next timer
clock cycle, even when the timer is stopped. This feature allows OCR2x to be initialized to the same
value as TCNT2 without triggering an interrupt when the timer/counter clock is enabled.
ATmega48PA/88PA/168PA
8-bit Timer/Counter2 (TC2) with PWM and A...
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 203