Datasheet

Figure 21-1. T1/T0 Pin Sampling
Tn_sync
(To Clock
Select Logic)
Edge DetectorSynchronization
D QD Q
LE
D Q
Tn
clk
I/O
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an
edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one
system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to ensure
correct sampling. The external clock must be guaranteed to have less than half the system clock
frequency (f
Tn
< f
clk_I/O
/2) given a 50% duty cycle. Since the edge detector uses sampling, the maximum
frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem).
However, due to variation of the system clock frequency and duty cycle caused by the tolerances of the
oscillator source (crystal, resonator, and capacitors), it is recommended that maximum frequency of an
external clock source is less than f
clk_I/O
/2.5.
An external clock source cannot be prescaled.
Figure 21-2. Prescaler for Timer/Counter0 and Timer/Counter1(1)
CSn0
CSn1
CSn2
Synchronization
10-BIT T/C PRESCALER
Tn
clk
I/O
PSR10
Clear
C
K
/
8
CK/
2
5
6
C
K
/
6
4
C
K/
1
0
24
OFF
TIMER /COUNTERn CLOCK
SOURCE clk
Tn
Note: 1. The synchronization logic on the input pins (T1/T0) is shown in the block diagram above.
ATmega48PA/88PA/168PA
Timer/Counter 0, 1 Prescalers
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 196