Datasheet

21. Timer/Counter 0, 1 Prescalers
The 8-bit Timer/Counter0 (TC0) and the 16-bit Timer/Counter1 (TC1) share the same prescaler module,
but the timer/counters can have different prescaler settings. The following description applies to TC0,
TC1.
Related Links
19. 8-bit Timer/Counter0 (TC0) with PWM
20. 16-bit Timer/Counter1 (TC1) with PWM
21.1 Internal Clock Source
The timer/counter can be clocked directly by the system clock (by setting the CSn[2:0]=0x01). This
provides the fastest operation, with a maximum timer/counter clock frequency equal to system clock
frequency (f
CLK_I/O
). Alternatively, one of four taps from the prescaler can be used as a clock source. The
prescaled clock has a frequency of either f
CLK_I/O
/8, f
CLK_I/O
/64, f
CLK_I/O
/256, or f
CLK_I/O
/1024.
21.2 Prescaler Reset
The prescaler is free-running, i.e., it operates independently of the clock select logic of the timer/counter,
and it is shared by timer/counter1 and timer/counter0. Since the prescaler is not affected by the timer/
counter’s clock select, the state of the prescaler will have implications for situations where a prescaled
clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the
prescaler (0x06 > CSn[2:0] > 0x01). The number of system clock cycles from when the timer is enabled to
the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8,
64, 256, or 1024).
It is possible to use the prescaler Reset for synchronizing the timer/counter to program execution.
However, care must be taken if the other timer/counter that shares the same prescaler also uses
prescaling. A prescaler Reset will affect the prescaler period for all timer/counters it is connected to.
21.3 External Clock Source
An external clock source applied to the T1/T0 pin can be used as timer/counter clock (clk
T1
/clk
T0
). The
T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized
(sampled) signal is then passed through the edge detector. See the block diagram of the T1/T0
synchronization and edge detector logic below. The registers are clocked at the positive edge of the
internal system clock (clk
I/O
). The latch is transparent in the high period of the internal system clock.
The edge detector generates one clk
T1
/clk
T0
pulse for each positive (CSn[2:0]=0x7) or negative
(CSn[2:0]=0x6) edge it detects.
ATmega48PA/88PA/168PA
Timer/Counter 0, 1 Prescalers
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 195