Datasheet

20.15.3 TC1 Control Register C

Name: TCCR1C

Offset: 0x82

Reset: 0x00

Property: -

Bit 7 6 5 4 3 2 1 0

FOC1A FOC1B

Access

R/W R/W

Reset 0 0

Bits 6, 7 – FOC1 Force Output Compare for Channel B and A

The FOC1A/FOC1B bits are only active when the WGM1[3:0] bits specifies a non-PWM mode. When

writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the waveform

generation unit. The OC1A/OC1B output is changed according to its COM1x[1:0] bits setting. Note that

the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x[1:0]

bits that determine the effect of the forced compare.

A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on

Compare Match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero.

ATmega48PA/88PA/168PA

16-bit Timer/Counter1 (TC1) with PWM

Datasheet Complete

DS40002011A-page 188