Datasheet

Mode WGM1[3] WGM1[2]
(CTC1)
(1)
WGM1[1]
(PWM1[1])
(1)
WGM1[0]
(PWM1[0])
(1)
Timer/
Counter
Mode of
Operation
TOP Update of
OCR1x at
TOV1 Flag
Set on
2 0 0 1 0 PWM, Phase
Correct, 9-bit
0x01FF TOP BOTTOM
3 0 0 1 1 PWM, Phase
Correct, 10-bit
0x03FF TOP BOTTOM
4 0 1 0 0 CTC OCR1A Immediate MAX
5 0 1 0 1 Fast PWM, 8-
bit
0x00FF BOTTOM TOP
6 0 1 1 0 Fast PWM, 9-
bit
0x01FF BOTTOM TOP
7 0 1 1 1 Fast PWM, 10-
bit
0x03FF BOTTOM TOP
8 1 0 0 0 PWM, Phase
and Frequency
Correct
ICR1 BOTTOM BOTTOM
9 1 0 0 1 PWM, Phase
and Frequency
Correct
OCR1A BOTTOM BOTTOM
10 1 0 1 0 PWM, Phase
Correct
ICR1 TOP BOTTOM
11 1 0 1 1 PWM, Phase
Correct
OCR1A TOP BOTTOM
12 1 1 0 0 CTC ICR1 Immediate MAX
13 1 1 0 1 Reserved - - -
14 1 1 1 0 Fast PWM ICR1 BOTTOM TOP
15 1 1 1 1 Fast PWM OCR1A BOTTOM TOP
Note:
1. The CTC1 and PWM1[1:0] bit definition names are obsolete. Use the WGM1[3:0] definitions.
However, the functionality and location of these bits are compatible with previous versions of the
timer.
ATmega48PA/88PA/168PA
16-bit Timer/Counter1 (TC1) with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 185