Datasheet

20.15.1 TC1 Control Register A
Name: TCCR1A
Offset: 0x80
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
COM1A[1:0] COM1B[1:0] WGM1[1:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 4:5, 6:7 – COM1 Compare Output Mode for Channel
The COM1A[1:0] and COM1B[1:0] control the output compare pins (OC1A and OC1B respectively)
behavior. If one or both of the COM1A[1:0] bits are written to one, the OC1A output overrides the normal
port functionality of the I/O pin it is connected to. If one or both of the COM1B[1:0] bit are written to one,
the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note
that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order
to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x[1:0] bits is dependent on
the WGM1[3:0] bits setting. The table below shows the COM1x[1:0] bit functionality when the WGM1[3:0]
bits are set to a Normal or a CTC mode (non-PWM).
Table 20-3. Compare Output Mode, Non-PWM
COM1A[1]/
COM1B[1]
COM1A[0]/
COM1B[0]
Description
0 0 Normal port operation, OC1A/OC1B disconnected.
0 1 Toggle OC1A/OC1B on compare match.
1 0 Clear OC1A/OC1B on compare match (Set output to low
level).
1 1 Set OC1A/OC1B on compare match (Set output to high
level).
The table below shows the COM1x[1:0] bit functionality when the WGM1[3:0] bits are set to the fast PWM
mode.
Table 20-4. Compare Output Mode, Fast PWM
COM1A[1]/
COM1B[1]
COM1A[0]/
COM1B[0]
Description
0 0 Normal port operation, OC1A/OC1B disconnected.
0 1 WGM1[3:0] = 14 or 15: Toggle OC1A on compare match, OC1B
disconnected (normal port operation). For all other WGM1
settings, normal port operation, OC1A/OC1B disconnected.
ATmega48PA/88PA/168PA
16-bit Timer/Counter1 (TC1) with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 183