Datasheet

Figure 20-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
clk_I/O
/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)
Note: The “n” in the register and bit names indicates the device number (n = 1 for timer/counter 1), and
the “x” indicates output compare unit (A/B).
The next figure shows the count sequence close to TOP in various modes. When using phase and
frequency correct PWM mode the OCR1x is updated at BOTTOM. The timing diagrams will be the same,
but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies
for modes that set the TOV1 flag at BOTTOM.
Figure 20-12. Timer/Counter Timing Diagram, no Prescaling.
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx Value
New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
Tn
(clk
I/O
/1)
clk
I/O
Note: The “n” in the register and bit names indicates the device number (n = 1 for timer/counter 1), and
the “x” indicates output compare unit (A/B).
The next figure shows the same timing data, but with the prescaler enabled.
ATmega48PA/88PA/168PA
16-bit Timer/Counter1 (TC1) with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 181