Datasheet


OCnxPFCPWM
=

clk_I/O
2    TOP
Note:
• The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and
the “x” indicates output compare unit (A/B).
• N represents the prescale divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x register represent special cases when generating a PWM waveform
output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be
continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For
inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value
(WGM1[3:0]=0x9) and COM1A[1:0]=0x1, the OC1A output will toggle with a 50% duty cycle.
20.13 Timer/Counter 0, 1 Prescalers
The 8-bit Timer/Counter0 (TC0) and the 16-bit Timer/Counter1 (TC1) share the same prescaler module,
but the timer/counters can have different prescaler settings. The following description applies to TC0,
TC1.
Related Links
19. 8-bit Timer/Counter0 (TC0) with PWM
20. 16-bit Timer/Counter1 (TC1) with PWM
20.14 Timer/Counter Timing Diagrams
The timer/counter is a synchronous design and the timer clock (clk
T1
) is therefore shown as a clock
enable signal in the following figures. The figures include information on when interrupt flags are set, and
when the OCR1x is updated with the OCR1x buffer value (only for modes utilizing double buffering). The
first figure shows a timing diagram for the setting of OCF1x.
Figure 20-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
clk
Tn
(clk
I/O
/1)
OCFnx
clk
I/O
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
Note: The “n” in the register and bit names indicates the device number (n = 1 for timer/counter 1), and
the “x” indicates output compare unit (A/B).
The next figure shows the same timing data, but with the prescaler enabled.
ATmega48PA/88PA/168PA
16-bit Timer/Counter1 (TC1) with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 180