Datasheet

(WGM1[3:0]=0xA), or the value in OCR1A (WGM1[3:0]=0xB). The counter has then reached the TOP and
changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing
diagram for the Phase Correct PWM mode is shown below, using OCR1A or ICR1 to define TOP. The
TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal lines on the TCNT1
slopes mark compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a
compare match occurs.
Figure 20-8. Phase Correct PWM Mode, Timing Diagram
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
Period
OCnx
OCnx
(COMnx[1:0]] = 0x2)
(COMnx[1:0] = 0x3)
Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and
the “x” indicates output compare unit (A/B).
The Timer/Counter Overflow flag (TOV1) is set each time the counter reaches BOTTOM. When either
OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same
timer clock cycle as the OCR1x registers are updated with the double buffer value (at TOP). The interrupt
flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the
value of all of the compare registers. If the TOP value is lower than any of the compare registers, a
compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP
values, the unused bits are masked to zero when any of the OCR1x registers is written. As illustrated by
the third period in the timing diagram, changing the TOP actively while the Timer/Counter is running in the
phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of
update of the OCR1x. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP.
This implies that the length of the falling slope is determined by the previous TOP value, while the length
of the rising slope is determined by the new TOP value. When these two values differ the two slopes of
the period will differ in length. The difference in length gives the unsymmetrical result on the output.
It is recommended to use the Phase and Frequency Correct mode instead of the Phase Correct mode
when changing the TOP value while the Timer/Counter is running. When using a static TOP value, there
are practically no differences between the two modes of operation.
ATmega48PA/88PA/168PA
16-bit Timer/Counter1 (TC1) with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 177