Datasheet

The timing diagram for the Fast PWM mode using OCR1A or ICR1 to define TOP is shown below. The
TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal lines on the TCNT1
slopes mark compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a
compare match occurs.
Figure 20-7. Fast PWM Mode, Timing Diagram
TCNTn
OCRnx/TOP Update and
TOVn Interrupt Flag Set and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 7
Period
2 3 4 5 6 8
OCnx
OCnx
(COMnx[1:0] = 0x2)
(COMnx[1:0] = 0x3)
Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and
the “x” indicates output compare unit (A/B).
The Timer/Counter Overflow flag (TOV1) is set each time the counter reaches TOP. In addition, when
either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag is set at the same timer
clock cycle TOV1 is set. If one of the interrupts are enabled, the interrupt handler routine can be used for
updating the TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the
value of all of the Compare registers. If the TOP value is lower than any of the Compare registers, a
compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP
values the unused bits are masked to zero when any of the OCR1x registers are written.
The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value.
The ICR1 register is not double buffered. This means that if ICR1 is changed to a low value when the
counter is running with none or a low prescaler value, there is a risk that the new ICR1 value written is
lower than the current value of TCNT1. As result, the counter will miss the compare match at the TOP
value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at
0x0000 before the compare match can occur. The OCR1A Register, however, is double buffered. This
feature allows the OCR1A I/O location to be written any time. When the OCR1A I/O location is written the
value written will be put into the OCR1A Buffer register. The OCR1A Compare register will then be
updated with the value in the Buffer register at the next timer clock cycle the TCNT1 matches TOP. The
update is performed at the same timer clock cycle as the TCNT1 is cleared and the TOV1 flag is set.
Using the ICR1 register for defining TOP works well when using fixed TOP values. By using ICR1, the
OCR1A is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency
ATmega48PA/88PA/168PA
16-bit Timer/Counter1 (TC1) with PWM
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Datasheet Complete
DS40002011A-page 175