Datasheet

An interrupt can be generated at each time the counter value reaches the TOP value by either using the
OCF1A or ICF1 flag, depending on the actual CTC mode. If the interrupt is enabled, the interrupt handler
routine can be used for updating the TOP value.
Note: Changing TOP to a value close to BOTTOM while the counter is running must be done with care
since the CTC mode does not provide double buffering. If the new value written to OCR1A is lower than
the current value of TCNT1, the counter will miss the compare match. The counter will then count to its
maximum value (0xFF for an 8-bit counter, 0xFFFF for a 16-bit counter) and wrap around starting at 0x00
before the compare match will occur.
In many cases, this feature is not desirable. An alternative will then be to use the Fast PWM mode using
OCR1A for defining TOP (WGM1[3:0]=0xF), since the OCR1A then will be double buffered.
For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on
each compare match by setting the Compare Output mode bits to toggle mode (COM1A[1:0]=0x1). The
OC1A value will not be visible on the port pin unless the data direction for the pin is set to output
(DDR_OC1A=1). The waveform generated will have a maximum frequency of f
OC1A
= f
clk_I/O
/2 when
OCR1A is set to ZERO (0x0000). The waveform frequency is defined by the following equation:

OCnA
=

clk_I/O
2   
1 + OCRnA
Note:
• The “n” indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output
Compare unit (A/B).
• N represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the Timer Counter TOV flag is set in the same timer clock cycle that
the counter counts from MAX to 0x0000.
20.12.3 Fast PWM Mode
The Fast Pulse Width Modulation or Fast PWM modes (modes 5, 6, 7, 14, and 15, WGM1[3:0]= 0x5, 0x6,
0x7, 0xE, 0xF) provide a high frequency PWM waveform generation option. The Fast PWM differs from
the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then
restarts from BOTTOM.
In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match
between TCNT1 and OCR1x and set at BOTTOM. In inverting Compare Output mode output is set on
compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of
the Fast PWM mode can be twice as high as the phase correct, and phase and frequency correct PWM
modes that use dual-slope operation. This high frequency makes the Fast PWM mode well suited for
power regulation, rectification, and DAC applications. High frequency allows physically small sized
external components (coils, capacitors), hence reduces total system cost.
The PWM resolution for Fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A.
The minimum resolution allowed is 2-bit (ICR1 or OCR1A register set to 0x0003), and the maximum
resolution is 16-bit (ICR1 or OCR1A registers set to MAX). The PWM resolution in bits can be calculated
by using the following equation:

FPWM
=
log TOP+1
log 2
In Fast PWM mode the counter is incremented until the counter value matches either one of the fixed
values 0x00FF, 0x01FF, or 0x03FF (WGM1[3:0] = 0x5, 0x6, or 0x7), the value in ICR1 (WGM1[3:0]=0xE),
or the value in OCR1A (WGM1[3:0]=0xF). The counter is then cleared at the following timer clock cycle.
ATmega48PA/88PA/168PA
16-bit Timer/Counter1 (TC1) with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 174