Datasheet

bits. The TOP and BOTTOM signals are used by the waveform generator for handling the special cases
of the extreme values in some modes of operation, see 20.12 Modes of Operation.
A special feature of output compare unit A allows it to define the Timer/Counter TOP value (i.e., counter
resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms
generated by the waveform generator.
Below is a block diagram of the output compare unit. The elements of the block diagram that are not
directly a part of the output compare unit are gray shaded.
Figure 20-4. Output Compare Unit, Block Diagram
OCFnx (Int.Req.)
= (16-bit Comparator )
OCRnx Buffer (16-bit Register)
OCRnxH Buf. (8-bit)
OCnx
TEMP (8-bit)
DATA BUS (8-bit)
OCRnxL Buf. (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
COMnx[1:0]WGMn[3:0]
OCRnx (16-bit Register)
OCRnxH (8-bit) OCRnxL (8-bit)
Waveform Generator
TOP
BOTTOM
Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and
the “x” indicates output compare unit (A/B).
The OCR1x is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For
the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The
double buffering synchronizes the update of the OCR1x to either TOP or BOTTOM of the counting
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses,
thereby making the output glitch-free.
When double buffering is enabled, the CPU has access to the OCR1x Buffer register. When double
buffering is disabled, the CPU will access the OCR1x directly.
The content of the OCR1x (Buffer or Compare) register is only changed by a write operation (the Timer/
Counter does not update this register automatically as the TCNT1 and ICR1). Therefore OCR1x is not
read via the high byte temporary register (TEMP). However, it is good practice to read the low byte first as
when accessing other 16-bit registers. Writing the OCR1x must be done via the TEMP register since the
compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be written first. When the
high byte I/O location is written by the CPU, the TEMP register will be updated by the value written. Then
ATmega48PA/88PA/168PA
16-bit Timer/Counter1 (TC1) with PWM
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Datasheet Complete
DS40002011A-page 170