Datasheet

19.9.3 TC0 Interrupt Mask Register

Name: TIMSK0

Offset: 0x6E

Reset: 0x00

Property: -

Bit 7 6 5 4 3 2 1 0

OCIE0B OCIE0A TOIE0

Access

R/W R/W R/W

Reset 0 0 0

Bit 2 – OCIE0B Timer/Counter0, Output Compare B Match Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status register is set, the timer/counter

compare match B interrupt is enabled. The corresponding interrupt is executed if a compare match in

timer/counter occurs, i.e., when the OCF0B bit is set in 19.9.8 TIFR0.

Bit 1 – OCIE0A Timer/Counter0, Output Compare A Match Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status register is set, the timer/counter0

compare match A interrupt is enabled. The corresponding interrupt is executed if a compare match in

timer/counter0 occurs, i.e., when the OCF0A bit is set in 19.9.8 TIFR0.

Bit 0 – TOIE0 Timer/Counter0, Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status register is set, the timer/counter0 overflow

interrupt is enabled. The corresponding interrupt is executed if an overflow in timer/counter0 occurs, i.e.,

when the TOV0 bit is set in 19.9.8 TIFR0.

ATmega48PA/88PA/168PA

8-bit Timer/Counter0 (TC0) with PWM

Datasheet Complete

DS40002011A-page 155