Datasheet

19.9.1 TC0 Control Register A
Name: TCCR0A
Offset: 0x44
Reset: 0x00
Property: When addressing as I/O register: address offset is 0x24
Bit 7 6 5 4 3 2 1 0
COM0A[1:0] COM0B[1:0] WGM0[1:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 7:6 – COM0A[1:0] Compare Output Mode for Channel A
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A[1:0] bits are
set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However,
note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to
enable the output driver.
When OC0A is connected to the pin, the function of the COM0A[1:0] bits depends on the WGM0[2:0] bit
setting. The table below shows the COM0A[1:0] bit functionality when the WGM0[2:0] bits are set to a
normal or CTC mode (non-PWM).
Table 19-3. Compare Output Mode, Non-PWM
COM0A[1] COM0A[0] Description
0 0 Normal port operation, OC0A disconnected.
0 1 Toggle OC0A on compare match.
1 0 Clear OC0A on compare match.
1 1 Set OC0A on compare match.
The table below shows the COM0A[1:0] bit functionality when the WGM0[1:0] bits are set to fast PWM
mode.
Table 19-4. Compare Output Mode, Fast PWM
(1)
COM0A[1] COM0A[0] Description
0 0 Normal port operation, OC0A disconnected.
0 1 WGM0[2:0]: Normal port operation, OC0A disconnected.
WGM0[2:1]: Toggle OC0A on compare match.
1 0 Clear OC0A on compare match, set OC0A at BOTTOM (Non-inverting mode).
1 1 Set OC0A on compare match, clear OC0A at BOTTOM (Inverting mode).
Note:
1. A special case occurs when OCR0A equals TOP and COM0A[1] is set. In this case the compare
match is ignored, but the set or clear is done at BOTTOM. Refer to 19.7.3 Fast PWM Mode for
details.
ATmega48PA/88PA/168PA
8-bit Timer/Counter0 (TC0) with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 150