Datasheet

Table 19-1. Definitions

Constant Description

BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00 for 8-bit counters, or 0x0000

for 16-bit counters).

MAX The counter reaches its Maximum when it becomes 0xFF (decimal 255, for 8-bit counters) or

0xFFFF (decimal 65535, for 16-bit counters).

TOP The counter reaches the TOP when it becomes equal to the highest value in the count

sequence. The TOP value can be assigned to be the fixed value MAX or the value stored in

the OCR0A Register. The assignment is dependent on the mode of operation.

19.2.2 Registers

The Timer/Counter 0 register (TCNT0) and Output Compare TC0x registers (OCR0x) are 8-bit registers.

Interrupt request (abbreviated to Int.Req. in the block diagram) signals are all visible in the Timer Interrupt

Flag Register 0 (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register 0

(TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

The timer/counter (TC) can be clocked internally, via the prescaler, or by an external clock source on the

T0 pin. The clock select logic block controls which clock source and edge are used by the timer/counter

to increment (or decrement) its value. The TC is inactive when no clock source is selected. The output

from the clock select logic is referred to as the timer clock (clk

The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the timer/

counter value at all times. The result of the compare can be used by the waveform generator to generate

a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). See 19.5 Output

Compare Unit for details. The compare match event will also set the Compare Flag (OCF0A or OCF0B),

which can be used to generate an output compare interrupt request.