Datasheet

18.4.1 MCU Control Register
Name: MCUCR
Offset: 0x55
Reset: 0x00
Property: When addressing as I/O register: address offset is 0x35
The MCU Control register controls the placement of the interrupt vector table in order to move interrupts
between application and boot space. (For ATmega88PA and ATmega168PA )
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Bit 7 6 5 4 3 2 1 0
BODS BODSE PUD IVSEL IVCE
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 6 – BODS BOD Sleep
The BODS bit must be written to '1' in order to turn off BOD during sleep. Writing to the BODS bit is
controlled by a timed sequence and the enable bit BODSE. To disable BOD in relevant sleep modes, both
BODS and BODSE must first be written to '1'. Then, BODS must be written to '1' and BODSE must be
written to zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS
is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared
after three clock cycles.
Bit 5 – BODSE BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is
controlled by a timed sequence.
Bit 4 – PUD Pull-up Disable
When this bit is written to one, the pull ups in the I/O ports are disabled even if the DDxn and PORTxn
registers are configured to enable the pull ups ({DDxn, PORTxn} = 0b01).
Bit 1 – IVSEL Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Flash memory.
When this bit is set (one), the interrupt vectors are moved to the beginning of the boot loader section of
the Flash. The actual address of the start of the boot Flash section is determined by the BOOTSZ fuses.
To avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to
change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the
same cycle as IVCE is written, and interrupts remain disabled until after the instruction following the write
to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status register
is unaffected by the automatic disabling.
ATmega48PA/88PA/168PA
I/O-Ports
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 125