Datasheet

17.2.4 Pin Change Interrupt Control Register
Name: PCICR
Offset: 0x68
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
PCIE2 PCIE1 PCIE0
Access
R/W R/W R/W
Reset 0 0 0
Bit 2 – PCIE2 Pin Change Interrupt Enable 2
When the PCIE2 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 2 is
enabled. Any change on any enabled PCINT[23:16] pin will cause an interrupt. The corresponding
interrupt of pin change interrupt request is executed from the PCI2 Interrupt Vector. PCINT[23:16] pins
are enabled individually by the PCMSK2 register.
Bit 1 – PCIE1 Pin Change Interrupt Enable 1
When the PCIE1 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 1 is
enabled. Any change on any enabled PCINT[14:8] pin will cause an interrupt. The corresponding interrupt
of pin change interrupt request is executed from the PCI1 Interrupt Vector. PCINT[14:8] pins are enabled
individually by the PCMSK1 register.
Bit 0 – PCIE0 Pin Change Interrupt Enable 0
When the PCIE0 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 0 is
enabled. Any change on any enabled PCINT[7:0] pin will cause an interrupt. The corresponding interrupt
of pin change interrupt request is executed from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled
individually by the PCMSK0 register.
ATmega48PA/88PA/168PA
EXTINT - External Interrupts
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 103