Datasheet

17.2.3 External Interrupt Flag Register

Name: EIFR

Offset: 0x3C

Reset: 0x00

Property: When addressing as I/O Register: address offset is 0x1C

When addressing I/O registers as data space using LD and ST instructions, the provided offset must be

used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an

I/O address offset within 0x00 - 0x3F.

Bit 7 6 5 4 3 2 1 0

INTF1 INTF0

Access

R/W R/W

Reset 0 0

Bit 1 – INTF1 External Interrupt Flag 1

When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 will be set. If the I-bit

in SREG and the INT1 bit in EIMSK are set, the MCU will jump to the corresponding interrupt vector. The

flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to

it. This flag is always cleared when INT1 is configured as a level interrupt.

Bit 0 – INTF0 External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 will be set. If the I-bit

in SREG and the INT0 bit in EIMSK are set, the MCU will jump to the corresponding interrupt vector. The

flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing '1' to

it. This flag is always cleared when INT0 is configured as a level interrupt.

ATmega48PA/88PA/168PA

EXTINT - External Interrupts

Datasheet Complete

DS40002011A-page 102