Datasheet

17.2.2 External Interrupt Mask Register
Name: EIMSK
Offset: 0x3D
Reset: 0x00
Property: When addressing as I/O register: address offset is 0x1D
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Bit 7 6 5 4 3 2 1 0
INT1 INT0
Access
R/W R/W
Reset 0 0
Bit 1 – INT1 External Interrupt Request 1 Enable
When the INT1 bit is set and the I-bit in the Status Register (SREG) is set, the external pin interrupt is
enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the External Interrupt Control
Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the
INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as
an output. The corresponding interrupt of external interrupt request 1 is executed from the INT1 interrupt
vector.
Bit 0 – INT0 External Interrupt Request 0 Enable
When the INT0 bit is set and the I-bit in the Status Register (SREG) is set, the external pin interrupt is
enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the External Interrupt Control
Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the
INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as
an output. The corresponding interrupt of external interrupt request 0 is executed from the INT0 interrupt
vector.
ATmega48PA/88PA/168PA
EXTINT - External Interrupts
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 101