Datasheet

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ATmega48PA/88PA/168PA

AVR

Microcontroller with picoPower

Technology

Introduction

The picoPower

Tmega48PA/88PA/168PA is a low-power CMOS 8-bit microcontroller based on the

AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega48PA/88PA/168PA achieves throughputs close to 1 MIPS

per MHz. This empowers system

designers to optimize the device for power consumption versus processing speed.

Feature

High Performance, Low-Power AVR

8-Bit Microcontroller Family

•

Advanced RISC Architecture

– 131 Powerful instructions

– Most single clock cycle execution

– 32 x 8 General purpose working registers

– Fully static operation

– Up to 20 MIPS throughput at 20 MHz

– On-chip 2-cycle multiplier

• High Endurance Nonvolatile Memory Segments

– 4K/8K/16K Bytes of in-system self-programmable Flash program memory

– 256/512/512 Bytes EEPROM

– 512/1K/1K Bytes internal SRAM

– Write/erase cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C

(1)

– Optional boot code section with independent lock bits

• In-system programming by on-chip boot program

• True read-while-write operation

– Programming lock for software security

• QTouch Library Support

– Capacitive touch buttons, sliders and wheels

– QTouch and QMatrix acquisition

– Up to 64 sense channels

• Peripheral Features

– Two 8-bit Timer/counters with separate prescaler and Compare mode

– One 16-bit Timer/counter with separate prescaler, Compare mode, and Capture mode

– Real time counter with separate oscillator

– Six PWM channels

Datasheet Complete

DS40002011A-page 1

Summary of content (495 pages)

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ATmega48PA/88PA/168PA AVR® Microcontroller with picoPower® Technology Introduction ® The picoPower ATmega48PA/88PA/168PA is a low-power CMOS 8-bit microcontroller based on the ® AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ® ATmega48PA/88PA/168PA achieves throughputs close to 1 MIPS per MHz. This empowers system designers to optimize the device for power consumption versus processing speed.
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ATmega48PA/88PA/168PA – – – – – – • • • • • • 8-channel 10-bit ADC in TQFP and QFN/MLF package • Temperature measurement 6-channel 10-bit ADC in PDIP package • Temperature measurement Two master/slave SPI serial interface One programmable serial USART One byte-oriented 2-wire serial interface (Philips I2C compatible) Programmable watchdog timer with separate on-chip oscillator – One on-chip analog comparator – Interrupt and wake-up on pin change Special Microcontroller Features – Power-on Reset and pr
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Table of Contents Introduction......................................................................................................................1 Feature............................................................................................................................ 1 1. Description...............................................................................................................10 2. Configuration Summary............................................................................
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ATmega48PA/88PA/168PA 13. System Clock and Clock Options............................................................................ 53 13.1. Clock Systems and Their Distribution........................................................................................ 53 13.2. Clock Sources............................................................................................................................ 54 13.3. Low-Power Crystal Oscillator.............................................................
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ATmega48PA/88PA/168PA 17.2. Register Description................................................................................................................... 99 18. I/O-Ports................................................................................................................ 108 18.1. 18.2. 18.3. 18.4. Overview.................................................................................................................................. 108 Ports as General Digital I/O..................
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ATmega48PA/88PA/168PA 22.6. Compare Match Output Unit.....................................................................................................204 22.7. Modes of Operation..................................................................................................................205 22.8. Timer/Counter Timing Diagrams.............................................................................................. 209 22.9. Asynchronous Operation of Timer/Counter2................................
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ATmega48PA/88PA/168PA 27. Analog Comparator (AC)....................................................................................... 309 27.1. Overview.................................................................................................................................. 309 27.2. Analog Comparator Multiplexed Input...................................................................................... 309 27.3. Register Description.................................................................
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ATmega48PA/88PA/168PA 32.7. Parallel Programming Parameters, Pin Mapping, and Commands..........................................369 32.8. Parallel Programming...............................................................................................................371 32.9. Serial Downloading.................................................................................................................. 378 33. Electrical Characteristics.................................................................
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ATmega48PA/88PA/168PA Microchip Devices Code Protection Feature............................................................... 492 Legal Notice.................................................................................................................493 Trademarks................................................................................................................. 493 Quality Management System Certified by DNV...........................................................
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ATmega48PA/88PA/168PA Description 1. Description ® The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in a single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
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ATmega48PA/88PA/168PA Configuration Summary 2. Configuration Summary Features ATmega48PA/88PA/168PA Pin Count 28/32 Flash (Bytes) 4K/8K/16K SRAM (Bytes) 512/1K/1K EEPROM (Bytes) 256/512/512 Interrupt Vector Size (instruction word/vector) 1/1/2 General Purpose I/O Lines 23 SPI 2 TWI (I2C) 1 USART 1 ADC 10-bit 15 kSPS ADC Channels 8 8-bit Timer/Counters 2 16-bit Timer/Counters 1 ATmega88PA and ATmega168PA support a real read-while-write self-programming mechanism.
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ATmega48PA/88PA/168PA Ordering Information 3. Ordering Information 3.1 ATmega48PA Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1) Operational Range 20 1.8 - 5.
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ATmega48PA/88PA/168PA Ordering Information 3.2 ATmega88PA Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1) Operational Range 20 1.8 - 5.
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ATmega48PA/88PA/168PA Ordering Information 3.3 ATmega168PA Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1) Operational Range 20 1.8 - 5.
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ATmega48PA/88PA/168PA Block Diagram 4. Block Diagram Figure 4-1. Block Diagram SRAM debugWire CPU OCD Clock generation XTAL1 / TOSC1 XTAL2 / TOSC2 32.768kHz XOSC 8MHz Calib RC External clock 16MHz LP XOSC VCC 128kHz int osc Power Supervision POR/BOD & RESET RESET GND ADC6,ADC7,PC[5:0] AREF ADC[7:0] AREF PD[7:0], PC[6:0], PB[7:0] PD3, PD2 PCINT[23:0] INT[1:0] PB1, PB2 PD5 PB0 OC1A/B T1 ICP1 PB3 PD3 OC2A OC2B © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Pin Configurations 5. 5.1 Pin Configurations Pin-out Figure 5-1.
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ATmega48PA/88PA/168PA Pin Configurations PD2 (INT0/PCINT18) PD1 (TXD/PCINT17) PD0 (RXD/PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) 28 27 26 25 24 23 22 Figure 5-2.
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ATmega48PA/88PA/168PA Pin Configurations PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) 29 28 27 Digital Analog Crystal/CLK PC2 (ADC2/PCINT10) PD0 (RXD/PCINT16) 30 Programming/debug 25 PD1 (TXD/PCINT17) 31 Ground 26 PD2 (INT0/PCINT18) 32 Power PC3 (ADC3/PCINT11) Figure 5-3.
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ATmega48PA/88PA/168PA Pin Configurations PD2 (INT0/PCINT18) PD1 (TXD/PCINT17) PD0 (RXD/PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) 32 31 30 29 28 27 26 25 Figure 5-4.
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ATmega48PA/88PA/168PA Pin Configurations 5.2 Pin Descriptions 5.2.1 VCC Digital supply voltage pin. 5.2.2 GND Ground. 5.2.3 Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated.
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ATmega48PA/88PA/168PA Pin Configurations 5.2.9 ADC[7:6] In the TQFP and VFQFN package, ADC[7:6] serve as analog inputs to the A/D converter. These pins are powered by the analog supply and serve as 10-bit ADC channels. © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA I/O Multiplexing 6. I/O Multiplexing Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the PORT I/O pins. Table 6-1.
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ATmega48PA/88PA/168PA I/O Multiplexing (32-pin 32UFBGA) Pin# (32-pin MLF/ TQFP) Pin# (28-pin MLF) Pin# (28-pin PIPD) Pin# PAD A3 29 25 1 PC6/ RESET PCINT14 B3 30 26 2 PD0 PCINT16 RXD0 A2 31 27 3 PD1 PCINT17 TXD0 A1 32 28 4 PD2 © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Resources 7. Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.microchip.com/design-centers/8-bit/microchip-avr-mcus. © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Data Retention 8. Data Retention Reliability qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C. © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA About Code Examples 9. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Confirm with the C compiler documentation for more details.
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ATmega48PA/88PA/168PA Capacitive Touch Sensing 10. 10.1 Capacitive Touch Sensing QTouch Library ® ® The QTouch library provides a simple to use solution to realize touch sensitive interfaces on most AVR ™ microcontrollers. The QTouch library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate QTouch library for the AVR microcontroller.
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ATmega48PA/88PA/168PA AVR CPU Core 11. AVR CPU Core 11.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must, therefore, be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 11-1.
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ATmega48PA/88PA/168PA AVR CPU Core address pointer for lookup tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status register is updated to reflect information about the result of the operation.
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ATmega48PA/88PA/168PA AVR CPU Core The Status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA AVR CPU Core 11.3.1 Status Register Name: Offset: Reset: Property: SREG 0x5F 0x00 When addressing as I/O Register: address offset is 0x3F When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA AVR CPU Core Bit 0 – C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. 11.4 General Purpose Register File The register file is optimized for the AVR Enhanced RISC instruction set.
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ATmega48PA/88PA/168PA AVR CPU Core Figure 11-3. The X-, Y-, and Z-registers 15 X-register 0 7 R26 YH YL 0 7 R28 ZH ZL 0 7 R31 0 0 R29 7 0 0 R27 7 15 Z-register XL 7 15 Y-register XH 0 0 R30 In the different addressing modes, these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). Related Links 36. Instruction Set Summary 11.
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ATmega48PA/88PA/168PA AVR CPU Core The AVR stack pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH register will not be present. © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA AVR CPU Core 11.5.1 Stack Pointer Register Low and High byte Name: Offset: Reset: Property: SPL and SPH 0x5D 0x4FF When addressing I/O registers as data space the offset address is 0x3D The SPL and SPH register pair represents the 16-bit value, SP. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
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ATmega48PA/88PA/168PA AVR CPU Core Figure 11-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch The following figure shows the internal timing concept for the register file. In a single clock cycle, an ALU operation using two register operands is executed and the result is stored back to the destination register.
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ATmega48PA/88PA/168PA AVR CPU Core hardware clears the corresponding interrupt flag. Interrupt flags can be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software.
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ATmega48PA/88PA/168PA AVR CPU Core 11.7.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles, the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the program counter is pushed onto the stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles.
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ATmega48PA/88PA/168PA AVR Memories 12. AVR Memories 12.1 Overview This section describes the different memory types in the device. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the device features an EEPROM Memory for data storage. All memory spaces are linear and regular. 12.2 In-System Reprogrammable Flash Program Memory The ATmega48PA/88PA/168PA contains 4K/8K/16Kbytes on-chip in-system reprogrammable Flash memory for program storage.
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ATmega48PA/88PA/168PA AVR Memories Figure 12-2. Program Memory Map ATmega88PA Program Memory 0x0000 Application Flash Section Boot Flash Section 0x0FFF Figure 12-3. Program Memory Map ATmega168PA Program Memory 0x0000 Application Flash Section Boot Flash Section 0x1FFF Related Links 31. Boot Loader Support – Read-While-Write Self-programming (BTLDR) 32. Memory Programming (MEMPROG) 11.6 Instruction Execution Timing 12.
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ATmega48PA/88PA/168PA AVR Memories The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the extended I/O space from 0x60 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The lower 768/1280/1280 data memory locations address both the register file, the I/O memory, extended I/O memory, and the internal data SRAM.
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ATmega48PA/88PA/168PA AVR Memories 12.3.1 Data Memory Access Times The internal data SRAM access is performed in two clkCPU cycles as described in the following Figure. Figure 12-6. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 12.4 Next Instruction EEPROM Data Memory The ATmega48PA/88PA/168PA contains 256/512/512B of data EEPROM memory.
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ATmega48PA/88PA/168PA AVR Memories 12.4.2 Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low.
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ATmega48PA/88PA/168PA AVR Memories 12.6 Register Description 12.6.1 Accessing 16-Bit Registers The AVR data bus is 8-bits wide, so accessing 16-bit registers requires atomic operations. These registers must be byte-accessed using two read or write operations. 16-bit registers are connected to the 8-bit bus and a temporary register using a 16-bit bus. For a write operation, the high byte of the 16-bit register must be written before the low byte. The high byte is then written into the temporary register.
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ATmega48PA/88PA/168PA AVR Memories 12.6.2 EEPROM Address Register Low and High Byte Name: Offset: Reset: Property: EEARL and EEARH 0x41 [ID-000004d0] 0xXX When addressing as I/O Register: address offset is 0x21 The EEARL and EEARH register pair represents the 16-bit value, EEAR. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
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ATmega48PA/88PA/168PA AVR Memories 12.6.3 EEPROM Data Register Name: Offset: Reset: Property: EEDR 0x40 [ID-000004d0] 0x00 When addressing as I/O Register: address offset is 0x20 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA AVR Memories 12.6.4 EEPROM Control Register Name: Offset: Reset: Property: Bit EECR 0x3F [ID-000004d0] 0x00 When addressing as I/O register: address offset is 0x1F 7 6 5 4 EEPM[1:0] Access Reset 3 2 1 0 EERIE EEMPE EEPE EERE R/W R/W R/W R/W R/W R/W x x 0 0 x 0 Bits 5:4 – EEPM[1:0] EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action will be triggered when writing EEPE.
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ATmega48PA/88PA/168PA AVR Memories 1. 2. 3. 4. 5. 6. Wait until EEPE becomes zero. Wait until SPMEN in SPMCSR becomes zero. Write new EEPROM address to EEAR (optional). Write new EEPROM data to EEDR (optional). Write a '1' to the EEMPE bit while writing a zero to EEPE in EECR. Within four clock cycles after setting EEMPE, write a '1' to EEPE. The EEPROM cannot be programmed during a CPU write to the Flash memory.
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ATmega48PA/88PA/168PA AVR Memories ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret C Code Example(1) void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
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ATmega48PA/88PA/168PA AVR Memories 12.6.5 GPIOR2 – General Purpose I/O Register 2 Name: Offset: Reset: Property: GPIOR2 0x4B [ID-000004d0] 0x00 When addressing as I/O Register: address offset is 0x2B When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA AVR Memories 12.6.6 GPIOR1 – General Purpose I/O Register 1 Name: Offset: Reset: Property: GPIOR1 0x4A [ID-000004d0] 0x00 When addressing as I/O Register: address offset is 0x2A When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA AVR Memories 12.6.7 GPIOR0 – General Purpose I/O Register 0 Name: Offset: Reset: Property: GPIOR0 0x3E [ID-000004d0] 0x00 When addressing as I/O Register: address offset is 0x1E When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA System Clock and Clock Options 13. System Clock and Clock Options 13.1 Clock Systems and Their Distribution The following figure illustrates the principal clock systems in the device and their distribution. All the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes. The clock systems are described in the following sections.
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ATmega48PA/88PA/168PA System Clock and Clock Options 13.1.1 CPU Clock – clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the general purpose register file, the Status register, and the data memory holding the stack pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. 13.1.
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ATmega48PA/88PA/168PA System Clock and Clock Options 13.2.1 Default Clock Source The device is shipped with internal RC oscillator at 8.0 MHz and with the fuse CKDIV8 programmed, resulting in 1.0 MHz system clock. The start-up time is set to maximum, and the time-out period is enabled: CKSEL=0010, SUT=10, CKDIV8=0. This default setting ensures that all users can make their desired clock source setting using any available programming interface. 13.2.
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ATmega48PA/88PA/168PA System Clock and Clock Options Figure 13-2. Crystal Oscillator Connections C2 XTAL2 C1 XTAL1 GND Note: XTALn share the same pins as TOSCn Related Links 13.3 Low-Power Crystal Oscillator 13.4 Full Swing Crystal Oscillator 13.5 Low-Frequency Crystal Oscillator 13.3 Low-Power Crystal Oscillator This crystal oscillator is a low-power oscillator, with reduced voltage swing on the XTAL2 output.
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ATmega48PA/88PA/168PA System Clock and Clock Options Frequency Range [MHz] CKSEL[3:1](2) Absolute limits for total capacitance of C1 and C2 [pF](4) 3.0 - 8.0 110 12 - 22 8.0 - 16.0 111 12 - 22 Note: 1. This is the recommended CKSEL settings for the difference frequency ranges. 2. This option should not be used with crystals, only with ceramic resonators. 3.
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ATmega48PA/88PA/168PA System Clock and Clock Options 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. Related Links 13.2.3 Clock Source Connections 13.4 Full Swing Crystal Oscillator 13.
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ATmega48PA/88PA/168PA System Clock and Clock Options Oscillator Source / Power Conditions Start-Up Time from Power-down and Power-save Additional Delay from Reset CKSEL0 SUT[1:0] (VCC = 5.0V) Crystal oscillator, fast rising power 16K CK 14CK + 4.1 ms 1 10 Crystal oscillator, slowly rising power 16K CK 14CK + 65 ms 1 11 Note: 1.
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ATmega48PA/88PA/168PA System Clock and Clock Options • • • • Ce - is optional external capacitors as described in Figure 13-2. Ci - is the pin capacitance in the above table. CL - is the load capacitance for a 32.768 kHz crystal specified by the crystal vendor. CS - is the total stray capacitance for one TOSC pin. Crystals specifying a load capacitance (CL) higher than 6pF require external capacitors applied as described in 13.3 Low-Power Crystal Oscillator.
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ATmega48PA/88PA/168PA System Clock and Clock Options Table 13-11. Internal Calibrated RC Oscillator Operating Modes Frequency Range(1) [MHz] CKSEL[3:0] 7.3 - 8.1 0010(2) Note: 1. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 fuse can be programmed in order to divide the internal frequency by 8. 2. The device is shipped with this option selected. When this oscillator is selected, start-up times are determined by the SUT fuses: Table 13-12.
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ATmega48PA/88PA/168PA System Clock and Clock Options Table 13-14. Start-Up Times for the 128kHz Internal Oscillator Power Conditions Start-Up Time from Power-Down and PowerSave Additional Delay from Reset SUT[1:0] BOD enabled 6 CK 14 CK 00 Fast rising power 6 CK 14 CK + 4 ms 01 14 CK + 65 ms 10 Slowly rising power 6 CK Reserved 13.8 11 External Clock To drive the device from an external clock source, EXTCLK should be driven as shown in the figure below.
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ATmega48PA/88PA/168PA System Clock and Clock Options When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in Reset during the changes.
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ATmega48PA/88PA/168PA System Clock and Clock Options be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, the exact time it takes to switch from one clock division to the other cannot be exactly predicted. From the time the Clock Prescaler Selection bits (CLKPS[3:0]) values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this interval, two active clock edges are produced.
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ATmega48PA/88PA/168PA System Clock and Clock Options 13.12.1 Oscillator Calibration Register Name: Offset: Reset: Property: Bit 7 OSCCAL 0x66 Device Specific Calibration Value - 6 5 4 3 2 1 0 CAL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 7:0 – CAL[7:0] Oscillator Calibration Value The oscillator calibration register is used to trim the calibrated internal RC oscillator to remove process variations away from the oscillator frequency.
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ATmega48PA/88PA/168PA System Clock and Clock Options 13.12.2 Clock Prescaler Register Name: Offset: Reset: Property: Bit 7 CLKPR 0x61 Refer to the bit description - 6 5 4 3 2 CLKPCE Access Reset 1 0 CLKPS[3:0] R/W R/W R/W R/W R/W 0 x x x x Bit 7 – CLKPCE Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero.
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ATmega48PA/88PA/168PA System Clock and Clock Options CLKPS[3:0] Clock Division Factor 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved Related Links 13.11 System Clock Prescaler © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Power Management and Sleep Modes 14. Power Management and Sleep Modes 14.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The device provides various sleep modes allowing the user to tailor the power consumption to the application requirements. When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods.
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ATmega48PA/88PA/168PA Power Management and Sleep Modes execution from the instruction following SLEEP. The contents of the register file and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during Sleep mode, the MCU wakes up and executes from the Reset vector. Related Links 13. System Clock and Clock Options 14.3 BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, the BOD is actively monitoring the power supply voltage during a sleep period.
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ATmega48PA/88PA/168PA Power Management and Sleep Modes • • • • • • • • Watchdog System Reset Watchdog Interrupt Brown-out Reset Two-wire Serial Interface Address Match Timer/Counter Interrupt SPM/EEPROM Ready Interrupt External Level Interrupt on INT Pin Change Interrupt Note: 1. Timer/Counter will only keep running in Asynchronous mode. Related Links 22. 8-bit Timer/Counter2 (TC2) with PWM and Asynchronous Operation 14.
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ATmega48PA/88PA/168PA Power Management and Sleep Modes If timer/counter2 is not running, the Power-Down mode is recommended instead of the Power-Save mode. The timer/counter2 can be clocked both synchronously and asynchronously in Power-Save mode. If timer/counter2 is not using the asynchronous clock, the timer/counter oscillator is stopped during sleep. If timer/counter2 is not using the synchronous clock, the clock source is stopped during sleep.
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ATmega48PA/88PA/168PA Power Management and Sleep Modes 14.11.2 Analog Comparator When entering Idle mode, the analog comparator should be disabled if not used. When entering ADC Noise Reduction mode, the analog comparator should be disabled. In other sleep modes, the analog comparator is automatically disabled. However, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep modes.
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ATmega48PA/88PA/168PA Power Management and Sleep Modes 18.2.5 Digital Input Enable and Sleep Modes 14.11.7 On-chip Debug System If the on-chip debug system is enabled by the fuse and the chip enters Sleep mode, the main clock source is enabled and hence always consumes power. In the deeper Sleep modes, this will contribute significantly to the total current consumption. 14.12 Register Description © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Power Management and Sleep Modes 14.12.1 Sleep Mode Control Register Name: Offset: Reset: Property: SMCR 0x53 0x00 When addressing as I/O Register: address offset is 0x33 The Sleep Mode Control register contains control bits for power management. When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used.
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ATmega48PA/88PA/168PA Power Management and Sleep Modes 14.12.2 MCU Control Register Name: Offset: Reset: Property: MCUCR 0x55 0x00 When addressing as I/O register: address offset is 0x35 The MCU Control register controls the placement of the interrupt vector table in order to move interrupts between application and boot space. (For ATmega88PA and ATmega168PA ) When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used.
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ATmega48PA/88PA/168PA Power Management and Sleep Modes Note: If interrupt vectors are placed in the boot loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the application section. If interrupt vectors are placed in the application section and Boot Lock bit BLB12 is programmed, interrupts are disabled while executing from the boot loader section.
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ATmega48PA/88PA/168PA Power Management and Sleep Modes 14.12.3 Power Reduction Register Name: Offset: Reset: Property: Bit Access Reset PRR 0x64 0x00 - 7 6 5 3 2 1 0 PRTWI0 PRTIM2 PRTIM0 4 PRTIM1 PRSPI0 PRUSART0 PRADC R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bit 7 – PRTWI0 Power Reduction TWI0 Writing a logic one to this bit shuts down the TWI 0 by stopping the clock to the module. When waking up the TWI again, the TWI should be reinitialized to ensure proper operation.
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ATmega48PA/88PA/168PA System Control and Reset 15. System Control and Reset 15.1 Resetting the AVR During Reset, all I/O registers are set to their initial values, and the program starts execution from the Reset vector. The instruction placed at the Reset vector must be an Absolute Jump instruction (JMP) to the reset handling routine for ATmega168PA. The instruction placed at the Reset vector must be a Relative Jump instruction (RJMP) to the reset handling routine for ATmega48PA and ATmega88PA.
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ATmega48PA/88PA/168PA System Control and Reset Figure 15-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER RSTDISBL Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 15.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The POR is activated whenever VCC is below the detection level.
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ATmega48PA/88PA/168PA System Control and Reset Figure 15-3. MCU Start-up, RESET Extended Externally VCC VPOT VRST RESET tTOUT TIME-OUT INTERNAL RESET 15.4 External Reset An external Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset.
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ATmega48PA/88PA/168PA System Control and Reset Figure 15-5. Brown-out Reset During Operation VCC VBOT- VBOT+ RESET tTOUT TIME-OUT INTERNALRESET 15.6 Watchdog System Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Figure 15-6. Watchdog System Reset During Operation CC CK 15.7 Internal Voltage Reference The device features an internal bandgap reference.
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ATmega48PA/88PA/168PA System Control and Reset 15.8 Watchdog Timer If the watchdog timer is not needed in the application, the module should be turned OFF. If the watchdog timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to 15.6 Watchdog System Reset for details on how to configure the watchdog timer. Features • • • • 15.8.
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ATmega48PA/88PA/168PA System Control and Reset The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time out configuration is as follows: 1. 2.
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ATmega48PA/88PA/168PA System Control and Reset Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialization routine, even if the Watchdog is not in use. The following code examples shows how to change the time-out value of the Watchdog Timer.
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ATmega48PA/88PA/168PA System Control and Reset 15.9.1 MCU Status Register Name: Offset: Reset: Property: MCUSR 0x54 [ID-000004d0] 0x00 When addressing as I/O Register: address offset is 0x34 To make use of the Reset flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.
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ATmega48PA/88PA/168PA System Control and Reset 15.9.2 WDTCSR – Watchdog Timer Control Register Name: Offset: Reset: Bit Access Reset WDTCSR 0x60 [ID-000004d0] 0x00 7 6 5 4 3 WDIF WDIE WDP[3] WDCE WDE 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 WDP[2:0] Bit 7 – WDIF Watchdog Interrupt Flag This bit is set when a time out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt.
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ATmega48PA/88PA/168PA System Control and Reset Bit 3 – WDE Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. Bits 2:0 – WDP[2:0] Watchdog Timer Prescaler 2, 1, and 0 The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running.
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ATmega48PA/88PA/168PA Interrupts 16. Interrupts This section describes the specifics of the interrupt handling of the device. For a general explanation of the AVR interrupt handling, refer to the description of Reset and Interrupt Handling. The interrupt vectors in ATmega48PA/88PA/168PA are generally the same, with the following differences: • • 16.1 Each interrupt vector occupies two instruction words ATmega168PA ; and one instruction word in ATmega48PA and ATmega88PA.
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ATmega48PA/88PA/168PA Interrupts Vector No Program Address Source Interrupts definition 23 0x0016 EE READY EEPROM Ready 24 0x0017 ANALOG COMP Analog Comparator 25 0x0018 TWI 2-wire Serial Interface (I2C) 26 0x0019 SPM READY Store Program Memory Ready The most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000C 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0
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ATmega48PA/88PA/168PA Interrupts Vector No Program Address(2) Source Interrupts definition 8 0x0007 TIMER2_COMPA Timer/Counter2 Compare Match A 9 0x0008 TIMER2_COMPB Timer/Coutner2 Compare Match B 10 0x0009 TIMER2_OVF Timer/Counter2 Overflow 11 0x000A TIMER1_CAPT Timer/Counter1 Capture Event 12 0x000B TIMER1_COMPA Timer/Counter1 Compare Match A 13 0x000C TIMER1_COMPB Timer/Coutner1 Compare Match B 14 0x000D TIMER1_OVF 15 0x000E TIMER0_COMPA Timer/Counter0 Compare Match A 16 0x00
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ATmega48PA/88PA/168PA Interrupts Note: 1. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000C 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 ; 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F ... Labels RESET: ...
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ATmega48PA/88PA/168PA Interrupts 0x0C03 0x0C04 0x0C05 out sei SPL,r16 ; Enable interrupts xxx When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the MCUCR.IVSEL is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels ; .org 0x0C00 0x0C00 0x0C01 0x0C02 ... 0x0C19 ; 0x0C1A RESET: 0x0C1B 0x0C1C 0x0C1D 0x0C1E 0x0C1F 16.3 Code Comments jmp jmp jmp ...
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ATmega48PA/88PA/168PA Interrupts Vector No Program Address(2) Source Interrupts definition 19 0x0024 USART_RX USART Rx Complete 20 0x0026 USART_UDRE USART Data Register Empty 21 0x0028 USART_TX USART Tx Complete 22 0x002A ADC ADC Conversion Complete 23 0x002C EE READY EEPROM Ready 24 0x002E ANALOG COMP Analog Comparator 25 0x0030 TWI 2-wire Serial Interface (I2C) 26 0x0032 SPM READY Store Program Memory Ready Note: 1.
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ATmega48PA/88PA/168PA Interrupts 0x0026 0x0028 0x002A 0x002C 0x002E 0x0030 0x0032 ; 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 ... RESET: ... jmp jmp jmp jmp jmp jmp jmp USART_UDRE USART_TXC ADC EE_RDY ANA_COMP TWI SPM_RDY ; ; ; ; ; ; ; ldi out ldi out sei ...
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ATmega48PA/88PA/168PA Interrupts 0x1C38 0x1C39 sei xxx ; Enable interrupts 16.4 Register Description 16.4.1 Moving Interrupts Between Application and Boot Space The MCU Control register controls the placement of the interrupt vector table (for ATmega88PA and ATmega168PA). © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Interrupts 16.4.2 MCU Control Register Name: Offset: Reset: Property: MCUCR 0x55 0x00 When addressing as I/O register: address offset is 0x35 The MCU Control register controls the placement of the interrupt vector table in order to move interrupts between application and boot space. (For ATmega88PA and ATmega168PA ) When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used.
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ATmega48PA/88PA/168PA Interrupts Note: If interrupt vectors are placed in the boot loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the application section. If interrupt vectors are placed in the application section and Boot Lock bit BLB12 is programmed, interrupts are disabled while executing from the boot loader section. Bit 0 – IVCE Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit.
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ATmega48PA/88PA/168PA EXTINT - External Interrupts 17. EXTINT - External Interrupts The external interrupts are triggered by the INT pins or any of the PCINT pins. Observe that, if enabled, the interrupts will trigger even if the INT or PCINT pins are configured as outputs. This feature provides a way of generating a software interrupt. The Pin Change Interrupt Request 2 (PCI2) will trigger if any enabled PCINT[23:16] pin toggles.
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ATmega48PA/88PA/168PA EXTINT - External Interrupts Figure 17-1. Timing of Pin Change Interrupts 0 PCINT[i] pin D Q pin_lat D Q pin_sync LE PCINT[i] bit (of PCMSKn) clk pcint_sync pcint_in[i] D 7 Q pcint_setflag D Q D Q PCIFn (interrupt flag) clk clk PCINT[i] pin pin_lat pin_sync pcint_in[i] pcint_syn pcint_setflag PCIFn Related Links 15. System Control and Reset 13.1 Clock Systems and Their Distribution 13. System Clock and Clock Options 17.
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ATmega48PA/88PA/168PA EXTINT - External Interrupts 17.2.1 External Interrupt Control Register A Name: Offset: Reset: Property: EICRA 0x69 0x00 - The External Interrupt Control Register A contains control bits for interrupt sense control. Bit 7 6 5 4 3 2 1 ISC1[1:0] Access Reset 0 ISC0[1:0] R/W R/W R/W R/W 0 0 0 0 Bits 3:2 – ISC1[1:0] Interrupt Sense Control 1 The external interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.
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ATmega48PA/88PA/168PA EXTINT - External Interrupts 17.2.2 External Interrupt Mask Register Name: Offset: Reset: Property: EIMSK 0x3D 0x00 When addressing as I/O register: address offset is 0x1D When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA EXTINT - External Interrupts 17.2.3 External Interrupt Flag Register Name: Offset: Reset: Property: EIFR 0x3C 0x00 When addressing as I/O Register: address offset is 0x1C When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA EXTINT - External Interrupts 17.2.4 Pin Change Interrupt Control Register Name: Offset: Reset: Property: Bit 7 PCICR 0x68 0x00 - 6 5 4 3 Access Reset 2 1 0 PCIE2 PCIE1 PCIE0 R/W R/W R/W 0 0 0 Bit 2 – PCIE2 Pin Change Interrupt Enable 2 When the PCIE2 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 2 is enabled. Any change on any enabled PCINT[23:16] pin will cause an interrupt.
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ATmega48PA/88PA/168PA EXTINT - External Interrupts 17.2.5 Pin Change Interrupt Flag Register Name: Offset: Reset: Property: PCIFR 0x3B 0x00 When addressing as I/O register: address offset is 0x1B When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA EXTINT - External Interrupts 17.2.6 Pin Change Mask Register 2 Name: Offset: Reset: Property: Bit 7 PCMSK2 0x6D 0x00 - 6 5 4 3 2 1 0 PCINT[23:16] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – PCINT[23:16] Pin Change Enable Mask Each PCINT[23:16]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
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ATmega48PA/88PA/168PA EXTINT - External Interrupts 17.2.7 Pin Change Mask Register 1 Name: Offset: Reset: Property: Bit 7 PCMSK1 0x6C 0x00 - 6 5 4 3 2 1 0 PCINT[14:8] Access Reset R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bits 6:0 – PCINT[14:8] Pin Change Enable Mask Each PCINT[15:8]-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[15:8] is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin.
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ATmega48PA/88PA/168PA EXTINT - External Interrupts 17.2.8 Pin Change Mask Register 0 Name: Offset: Reset: Property: Bit 7 PCMSK0 0x6B 0x00 - 6 5 4 3 2 1 0 PCINT[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – PCINT[7:0] Pin Change Enable Mask Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
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ATmega48PA/88PA/168PA I/O-Ports 18. I/O-Ports 18.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as an output) or enabling/disabling of pull-up resistors (if configured as an input).
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ATmega48PA/88PA/168PA I/O-Ports 18.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. The following figure shows the functional description of one I/O-port pin, here generically called Pxn. Figure 18-2.
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ATmega48PA/88PA/168PA I/O-Ports 18.2.2 Toggling the Pin Writing a '1' to PINxn toggles the value of PORTxn, independent on the value of DDRxn. The SBI instruction can be used to toggle one single bit in a port. 18.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
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ATmega48PA/88PA/168PA I/O-Ports Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn register at the succeeding positive clock edge.
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ATmega48PA/88PA/168PA I/O-Ports /* Insert nop for synchronization*/ __no_operation(); /* Read port pins */ i = PINB; ... 18.2.5 Digital Input Enable and Sleep Modes As shown in the figure of General Digital I/O, the digital input signal can be clamped to ground at the input of the Schmitt Trigger.
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ATmega48PA/88PA/168PA I/O-Ports Figure 18-5.
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ATmega48PA/88PA/168PA I/O-Ports Table 18-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
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ATmega48PA/88PA/168PA I/O-Ports Port Pin Alternate Functions PCINT7 (Pin Change Interrupt 7) PB6 XTAL1 (Chip Clock Oscillator pin 1 or External clock input) TOSC1 (Timer Oscillator pin 1) PCINT6 (Pin Change Interrupt 6) PB5 SCK (SPI Bus Master clock Input) PCINT5 (Pin Change Interrupt 5) PB4 MISO (SPI Bus Master Input/Slave Output) PCINT4 (Pin Change Interrupt 4) PB3 MOSI (SPI Bus Master Output/Slave Input) OC2A (Timer/Counter2 Output Compare Match A Output) PCINT3 (Pin Change Interrupt 3) PB2 SS
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ATmega48PA/88PA/168PA I/O-Ports – – TOSC2: Timer Oscillator pin 2. Used only if internal calibrated RC oscillator is selected as chip clock source, and the asynchronous timer is enabled by the correct setting in ASSR. When the AS2 bit in ASSR is set (one) and the EXCLK bit is cleared (zero) to enable asynchronous clocking of Timer/Counter2 using the crystal oscillator, pin PB7 is disconnected from the port, and becomes the inverting output of the oscillator amplifier.
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ATmega48PA/88PA/168PA I/O-Ports – PCINT3: Pin Change Interrupt source 3. The PB3 pin can serve as an external interrupt source. • SS/OC1B/PCINT2 – Port B, Bit 2 – SS: Slave Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. As slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2.
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ATmega48PA/88PA/168PA I/O-Ports Signal PB7/XTAL2/TOSC2/PCINT7(1) Name PB6/XTAL1/TOSC1/ PCINT6(1) PB5/SCK/PCINT5 PB4/MISO/PCINT4 DIEOE INTRC • EXTCK + AS2 + PCINT7 INTRC + AS2 + PCINT6 • • PCIE0 PCIE0 PCINT5 • PCIE0 PCINT4 • PCIE0 DIEOV (INTRC + EXTCK) • AS2 INTRC • AS2 1 1 DI PCINT6 INPUT PCINT5 INPUT PCINT4 INPUT SPI MSTR INPUT PCINT7 INPUT SCK INPUT AIO Oscillator Output Oscillator/Clock Input – – Notes: 1.
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ATmega48PA/88PA/168PA I/O-Ports Table 18-6.
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ATmega48PA/88PA/168PA I/O-Ports – – PCINT12: Pin Change Interrupt source 12. The PC4 pin can serve as an external interrupt source. PC4 can also be used as ADC input Channel 4. The ADC input channel 4 uses digital power. • ADC3/PCINT11 – Port C, Bit 3 – PC3 can also be used as ADC input Channel 3. The ADC input channel 3 uses analog power. – PCINT11: Pin Change Interrupt source 11. The PC3 pin can serve as an external interrupt source.
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ATmega48PA/88PA/168PA I/O-Ports Table 18-8. Overriding Signals for Alternate Functions in PC3...
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ATmega48PA/88PA/168PA I/O-Ports Port Pin Alternate Function PCINT20 (Pin Change Interrupt 20) PD3 INT1 (External Interrupt 1 Input) OC2B (Timer/Counter2 Output Compare Match B Output) PCINT19 (Pin Change Interrupt 19) PD2 INT0 (External Interrupt 0 Input) PCINT18 (Pin Change Interrupt 18) PD1 TXD (USART Output Pin) PCINT17 (Pin Change Interrupt 17) PD0 RXD (USART Input Pin) PCINT16 (Pin Change Interrupt 16) The alternate pin configuration is as follows: • AIN1/OC2B/PCINT23 – Port D, Bit 7 – AIN1:
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ATmega48PA/88PA/168PA I/O-Ports – (one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function. PCINT21: Pin Change Interrupt source 21. The PD5 pin can serve as an external interrupt source. • XCK/T0/PCINT20 – Port D, Bit 4 – XCK: USART external clock. – T0: Timer/Counter0 counter source. – PCINT20: Pin Change Interrupt source 20. The PD4 pin can serve as an external interrupt source. • INT1/OC2B/PCINT19 – Port D, Bit 3 – INT1: External Interrupt source 1.
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ATmega48PA/88PA/168PA I/O-Ports Signal Name PD7/AIN1 /PCINT23 PD6/AIN0/ OC0A/PCINT22 PD5/T1/OC0B/ PCINT21 PD4/XCK/ T0/PCINT20 PVOV 0 OC0A OC0B XCK OUTPUT DIEOE PCINT23 • PCIE2 PCINT22 • PCIE2 PCINT21 • PCIE2 PCINT20 • PCIE2 DIEOV 1 1 1 1 DI PCINT23 INPUT PCINT22 INPUT PCINT21 INPUT / T1 INPUT PCINT20 INPUT / XCK INPUT / T0 INPUT AIO AIN1 INPUT AIN0 INPUT – – Table 18-11. Overriding Signals for Alternate Functions in PD3...
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ATmega48PA/88PA/168PA I/O-Ports 18.4.1 MCU Control Register Name: Offset: Reset: Property: MCUCR 0x55 0x00 When addressing as I/O register: address offset is 0x35 The MCU Control register controls the placement of the interrupt vector table in order to move interrupts between application and boot space. (For ATmega88PA and ATmega168PA ) When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used.
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ATmega48PA/88PA/168PA I/O-Ports Note: If interrupt vectors are placed in the boot loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the application section. If interrupt vectors are placed in the application section and Boot Lock bit BLB12 is programmed, interrupts are disabled while executing from the boot loader section. Bit 0 – IVCE Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit.
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ATmega48PA/88PA/168PA I/O-Ports 18.4.2 Port B Data Register Name: Offset: Reset: Property: PORTB 0x25 0x00 When addressing as I/O Register: address offset is 0x05 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA I/O-Ports 18.4.3 Port B Data Direction Register Name: Offset: Reset: Property: DDRB 0x24 0x00 When addressing as I/O Register: address offset is 0x04 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA I/O-Ports 18.4.4 Port B Input Pins Address Name: Offset: Reset: Property: PINB 0x23 N/A When addressing as I/O Register: address offset is 0x03 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA I/O-Ports 18.4.5 Port C Data Register Name: Offset: Reset: Property: PORTC 0x28 0x00 When addressing as I/O Register: address offset is 0x08 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA I/O-Ports 18.4.6 Port C Data Direction Register Name: Offset: Reset: Property: DDRC 0x27 0x00 When addressing as I/O Register: address offset is 0x07 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA I/O-Ports 18.4.7 Port C Input Pins Address Name: Offset: Reset: Property: PINC 0x26 N/A When addressing as I/O Register: address offset is 0x06 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA I/O-Ports 18.4.8 Port D Data Register Name: Offset: Reset: Property: PORTD 0x2B 0x00 When addressing as I/O Register: address offset is 0x0B When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA I/O-Ports 18.4.9 Port D Data Direction Register Name: Offset: Reset: Property: DDRD 0x2A 0x00 When addressing as I/O Register: address offset is 0x0A When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA I/O-Ports 18.4.10 Port D Input Pins Address Name: Offset: Reset: Property: PIND 0x29 N/A When addressing as I/O Register: address offset is 0x09 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM 19. 8-bit Timer/Counter0 (TC0) with PWM 19.1 Features • • • • • • • 19.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM Figure 19-1. 8-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA Fixed TOP Value Waveform Generation = OCnB OCRnB TCCRnA 19.2.1 OCnB (Int.Req.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM Table 19-1. Definitions Constant Description BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00 for 8-bit counters, or 0x0000 for 16-bit counters). 19.2.2 MAX The counter reaches its Maximum when it becomes 0xFF (decimal 255, for 8-bit counters) or 0xFFFF (decimal 65535, for 16-bit counters). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM Figure 19-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count clear TCNTn direction Control Logic Edge Detector clkTn Tn ( From Prescaler ) bottom top Note: The “n” in the register and bit names indicates the device number (n = 0 for timer/counter 0), and the “x” indicates output compare unit (A/B). Table 19-2. Signal Description (Internal Signals) Signal Name Description count Increment or decrement TCNT0 by 1.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM according to operating mode set by the WGM02, WGM01, and WGM00 bits and Compare Output mode (COM0x[1:0]) bits. The maximum and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation. Figure 19-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn =(8-bit Comparator ) OCFnx (Int.Req.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM 19.5.3 Using the Output Compare Unit Since writing TCNTn in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNTn when using the output compare unit, independently of whether the timer/counter is running or not. If the value written to TCNTn equals the OCRnx value, the compare match will be missed, resulting in incorrect waveform generation.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM Figure 19-4. Compare Match Output Unit, Schematic COMnx[1] COMnx[0] FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O Note: The “n” in the register and bit names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates output compare unit (A/B).
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM 19.7 Modes of Operation The mode of operation determines the behavior of the timer/counter and the output compare pins. It is defined by the combination of the Waveform Generation mode bits and Compare Output mode (TCCR0A.WGM0[2:0]) bits in the Timer/Counter Control Registers A and B (TCCR0A.COM0x[1:0]). The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM An interrupt can be generated each time the counter value reaches the TOP value by setting the OCF0A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. Note: Changing TOP to a value close to BOTTOM while the counter is running must be done with care, since the CTC mode does not provide double buffering.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM Figure 19-6. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCnx (COMnx[1:0] = 0x2) OCnx (COMnx[1:0] = 0x3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM The counter counts repeatedly from BOTTOM to TOP, and then from TOP to BOTTOM. When WGM0[2:0]=0x1 TOP is defined as 0xFF. When WGM0[2:0]=0x5, TOP is defined as OCR0A. In noninverting Compare Output mode, the Output Compare (OC0x) bit is cleared on compare match between TCNT0 and OCR0x while up-counting and OC0x is set on the compare match while down-counting. In inverting Output Compare mode, the operation is inverted.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM �OCnxPCPWM = �clk_I/O � ⋅ 510 N represents the prescaler factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A register represent special cases when generating a PWM waveform output in the Phase Correct PWM mode: If the OCR0A register is written equal to BOTTOM, the output will be continuously low. If OCR0A is written to MAX, the output will be continuously high for non-inverted PWM mode.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM Figure 19-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Note: The “n” in the register and bit names indicates the device number (n = 0 for timer/counter 0), and the “x” indicates output compare unit (A/B). The next figure shows the setting of OCF0B in all modes and OCF0A in all modes (except CTC mode and PWM mode where OCR0A is TOP). Figure 19-10.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM Figure 19-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 OCRnx TOP BOTTOM BOTTOM + 1 TOP OCFnx Note: The “n” in the register and bit names indicates the device number (n = 0 for timer/counter 0), and the “x” indicates output compare unit (A/B). 19.9 Register Description © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM 19.9.1 TC0 Control Register A Name: Offset: Reset: Property: Bit TCCR0A 0x44 0x00 When addressing as I/O register: address offset is 0x24 7 6 5 COM0A[1:0] Access Reset 4 3 2 1 COM0B[1:0] 0 WGM0[1:0] R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 7:6 – COM0A[1:0] Compare Output Mode for Channel A These bits control the Output Compare pin (OC0A) behavior.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM The table below shows the COM0A[1:0] bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode. Table 19-5. Compare Output Mode, Phase Correct PWM Mode(1) COM0A[1] COM0A[0] Description 0 0 Normal port operation, OC0A disconnected. 0 1 WGM0[2:0]: Normal port operation, OC0A disconnected. WGM0[2:1]: Toggle OC0A on compare match. 1 0 Clear OC0A on compare match when up-counting. Set OC0A on compare match when down-counting.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM COM0B[1] COM0B[0] Description 1 0 Clear OC0B on compare match, set OC0B at BOTTOM, (Non-inverting mode). 1 1 Set OC0B on compare match, clear OC0B at BOTTOM, (Inverting mode). Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. Refer to 19.7.3 Fast PWM Mode for details.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM 19.9.2 TC0 Control Register B Name: Offset: Reset: Property: Bit Access Reset TCCR0B 0x45 0x00 When addressing as I/O register: address offset is 0x25 7 6 FOC0A FOC0B 5 4 WGM02 3 2 1 0 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 CS0[2:0] Bit 7 – FOC0A Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM CS0[2] CS0[1] CS0[0] Description 0 1 0 clkI/O/8 (from prescaler) 0 1 1 clkI/O/64 (from prescaler) 1 0 0 clkI/O/256 (from prescaler) 1 0 1 clkI/O/1024 (from prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM 19.9.3 TC0 Interrupt Mask Register Name: Offset: Reset: Property: Bit 7 TIMSK0 0x6E 0x00 - 6 5 4 3 Access Reset 2 1 0 OCIE0B OCIE0A TOIE0 R/W R/W R/W 0 0 0 Bit 2 – OCIE0B Timer/Counter0, Output Compare B Match Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status register is set, the timer/counter compare match B interrupt is enabled.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM 19.9.4 General Timer/Counter Control Register Name: Offset: Reset: Property: GTCCR 0x43 0x00 When addressing as I/O register: address offset is 0x23 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM 19.9.5 TC0 Counter Value Register Name: Offset: Reset: Property: TCNT0 0x46 0x00 When addressing as I/O Register: address offset is 0x26 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM 19.9.6 TC0 Output Compare Register A Name: Offset: Reset: Property: OCR0A 0x47 0x00 When addressing as I/O register: address offset is 0x27 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM 19.9.7 TC0 Output Compare Register B Name: Offset: Reset: Property: OCR0B 0x48 0x00 When addressing as I/O register: address offset is 0x28 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter0 (TC0) with PWM 19.9.8 TC0 Interrupt Flag Register Name: Offset: Reset: Property: TIFR0 0x35 0x00 When addressing as I/O Register: address offset is 0x15 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM 20. 16-bit Timer/Counter1 (TC1) with PWM 20.1 Overview The 16-bit timer/counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. A block diagram of the 16-bit timer/counter is shown below. CPU accessible I/O registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O register and bit locations are listed in 20.15 Register Description.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM Figure 20-1. 16-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM Table 20-1. Definitions Constant Description BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00 for 8-bit counters, or 0x0000 for 16-bit counters). 20.5 MAX The counter reaches its maximum when it becomes 0xFF (decimal 255, for 8-bit counters) or 0xFFFF (decimal 65535, for 16-bit counters). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM Accessing the low byte triggers the 16-bit read or write operation: When the low byte of a 16-bit register is written by the CPU, the high byte that is currently stored in TEMP and the low byte being written are both copied into the 16-bit register in the same clock cycle.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM Example 20-3. Assembly Code Example(1) TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret The assembly code example returns the TCNT1 value in the r17:r16 register pair. Example 20-4.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM } unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; Note: 1. The example code assumes that the part specific header file is included. For I/O registers located in extended I/O map, IN, OUT, SBIS, SBIC, CBI, and SBI instructions must be replaced with instructions that allow access to extended I/O.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM Table 20-2. Signal Description (Internal Signals) Signal Name Description Count Increment or decrement TCNT1 by 1. Direction Select between increment and decrement. Clear Clear TCNT1 (set all bits to zero). clkT1 Timer/counter clock. TOP Signalize that TCNT1 has reached maximum value. BOTTOM Signalize that TCNT1 has reached minimum value (zero).
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM Figure 20-3. Input Capture Unit Block Diagram for TC1 DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) WRITE ICRnL (8-bit) TCNTnH (8-bit) ICRn (16-bit Register) ACO TCNTnL (8-bit) TCNTn (16-bit Counter) ACIC Analog Comparator ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.) ICPn Note: The “n” in the register and bit names indicates the device number (n = 1 for timer/counter 1), and the “x” indicates output compare unit (A/B).
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The input capture flag must, therefore, be cleared after the change. Both the Input Capture Pin (ICP1) and the Analog Comparator Output (ACO) inputs are sampled using the same technique as for the T1 pin. The edge detector is identical.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM bits. The TOP and BOTTOM signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation, see 20.12 Modes of Operation. A special feature of output compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the waveform generator.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM when the low byte (OCR1xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x in the same system clock cycle. Related Links 20.6 Accessing 16-bit Timer/Counter Registers 20.10.1 Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (TCCR1C.FOC1x) bit.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM Figure 20-5. Compare Match Output Unit, Schematic COMnx[1] COMnx[0] FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates output compare unit (A/B). The general I/O port function is overridden by the Output Compare (OC1x) from the waveform generator if either of the TCCR1A.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM Related Links 20.14 Timer/Counter Timing Diagrams 20.11 Compare Match Output Unit 20.12.1 Normal Mode The simplest mode of operation is the Normal mode (TCCR1A.WGM1[3:0]=0x0). In this mode, the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX=0xFFFF) and then restarts from BOTTOM=0x0000.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag, depending on the actual CTC mode. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. Note: Changing TOP to a value close to BOTTOM while the counter is running must be done with care since the CTC mode does not provide double buffering.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM The timing diagram for the Fast PWM mode using OCR1A or ICR1 to define TOP is shown below. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal lines on the TCNT1 slopes mark compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. Figure 20-7.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In Fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Writing the COM1x[1:0] bits to 0x2 will produce an inverted PWM and a non-inverted PWM output can be generated by writing the COM1x[1:0] to 0x3.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM (WGM1[3:0]=0xA), or the value in OCR1A (WGM1[3:0]=0xB). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the Phase Correct PWM mode is shown below, using OCR1A or ICR1 to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM In Phase Correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Writing COM1x[1:0] bits to 0x2 will produce a non-inverted PWM. An inverted PWM output can be generated by writing the COM1x[1:0] to 0x3. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x).
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM Figure 20-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx[1:0] = 0x2) OCnx (COMnx[1:0] = 0x3) Period 1 2 3 4 Note: The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates output compare unit (A/B).
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM �OCnxPFCPWM = �clk_I/O 2 ⋅ � ⋅ TOP Note: • The “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates output compare unit (A/B). • N represents the prescale divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM Figure 20-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Note: The “n” in the register and bit names indicates the device number (n = 1 for timer/counter 1), and the “x” indicates output compare unit (A/B). The next figure shows the count sequence close to TOP in various modes.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM Figure 20-13.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM 20.15.1 TC1 Control Register A Name: Offset: Reset: Property: Bit TCCR1A 0x80 0x00 - 7 6 5 COM1A[1:0] Access Reset 4 3 2 1 COM1B[1:0] 0 WGM1[1:0] R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 4:5, 6:7 – COM1 Compare Output Mode for Channel The COM1A[1:0] and COM1B[1:0] control the output compare pins (OC1A and OC1B respectively) behavior.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM COM1A[1]/ COM1B[1] COM1A[0]/ COM1B[0] Description 1 0 Clear OC1A/OC1B on compare match, set OC1A/OC1B at BOTTOM (Non-inverting mode) 1 1 Set OC1A/OC1B on compare match, clear OC1A/OC1B at BOTTOM (Inverting mode) Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A[1]/COM1B[1] is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. Refer to 20.12.3 Fast PWM Mode for details.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM Mode WGM1[3] WGM1[2] (CTC1)(1) WGM1[1] WGM1[0] (PWM1[1])(1) (PWM1[0])(1) Timer/ Counter TOP Update of TOV1 Flag OCR1x at Set on Mode of Operation 2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM 3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0 1 0 0 CTC OCR1A Immediate MAX 5 0 1 0 1 Fast PWM, 8bit 0x00FF BOTTOM TOP 6 0 1 1 0 Fast PWM, 9bit 0x01FF BOTTOM TOP 7 0 1 1 1 Fast P
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM 20.15.2 TC1 Control Register B Name: Offset: Reset: Property: Bit Access Reset TCCR1B 0x81 0x00 - 7 6 4 3 ICNC1 ICES1 5 WGM13 WGM12 2 1 0 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 CS1[2:0] Bit 7 – ICNC1 Input Capture Noise Canceler Writing this bit to '1' activates the input capture noise canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP1) is filtered.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM CS1[2] CS1[1] CS1[0] 1 1 0 External clock source on T1 pin. Clock on falling edge. 1 1 1 External clock source on T1 pin. Clock on rising edge. © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM 20.15.3 TC1 Control Register C Name: Offset: Reset: Property: Bit Access Reset TCCR1C 0x82 0x00 - 7 6 FOC1A FOC1B R/W R/W 0 0 5 4 3 2 1 0 Bits 6, 7 – FOC1 Force Output Compare for Channel B and A The FOC1A/FOC1B bits are only active when the WGM1[3:0] bits specifies a non-PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the waveform generation unit.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM 20.15.4 TC1 Counter Value Low and High byte Name: Offset: Reset: Property: TCNT1L and TCNT1H 0x84 0x00 - The TCNT1L and TCNT1H register pair represents the 16-bit value, TCNT1. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM 20.15.5 Input Capture Register 1 Low and High byte Name: Offset: Reset: Property: ICR1L and ICR1H 0x86 0x00 - The ICR1L and ICR1H register pair represents the 16-bit value, ICR1. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM 20.15.6 Output Compare Register 1 A Low and High byte Name: Offset: Reset: Property: OCR1AL and OCR1AH 0x88 0x00 - The OCR1AL and OCR1AH register pair represents the 16-bit value, OCR1A. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM 20.15.7 Output Compare Register 1 B Low and High byte Name: Offset: Reset: Property: OCR1BL and OCR1BH 0x8A 0x00 - The OCR1BL and OCR1BH register pair represents the 16-bit value, OCR1B. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM 20.15.8 Timer/Counter 1 Interrupt Mask Register Name: Offset: Reset: Property: Bit 7 TIMSK1 0x6F 0x00 - 6 Access Reset 2 1 0 ICIE1 5 4 3 OCIE1B OCIE1A TOIE1 R/W R/W R/W R/W 0 0 0 0 Bit 5 – ICIE1 Timer/Counter 1, Input Capture Interrupt Enable When this bit is written to '1', and the I-flag in the Status register is set (interrupts globally enabled), the timer/counter 1 input capture interrupt is enabled.
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ATmega48PA/88PA/168PA 16-bit Timer/Counter1 (TC1) with PWM 20.15.9 TC1 Interrupt Flag Register Name: Offset: Reset: Property: TIFR1 0x36 0x00 When addressing as I/O register: address offset is 0x16 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA Timer/Counter 0, 1 Prescalers 21. Timer/Counter 0, 1 Prescalers The 8-bit Timer/Counter0 (TC0) and the 16-bit Timer/Counter1 (TC1) share the same prescaler module, but the timer/counters can have different prescaler settings. The following description applies to TC0, TC1. Related Links 19. 8-bit Timer/Counter0 (TC0) with PWM 20. 16-bit Timer/Counter1 (TC1) with PWM 21.
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ATmega48PA/88PA/168PA Timer/Counter 0, 1 Prescalers Figure 21-1. T1/T0 Pin Sampling D Tn Q D Q D Tn_sync (To Clock Select Logic) Q LE clk I/O Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated.
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ATmega48PA/88PA/168PA Timer/Counter 0, 1 Prescalers 21.4.1 General Timer/Counter Control Register Name: Offset: Reset: Property: GTCCR 0x43 0x00 When addressing as I/O register: address offset is 0x23 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... 22. 8-bit Timer/Counter2 (TC2) with PWM and Asynchronous Operation 22.1 Features • • • • • • • 22.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... Figure 22-1. 8-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn = =0 OCnA (Int.Req.) Waveform Generation = OCnA OCRnA DATA BUS Fixed TOP Value OCnB (Int.Req.) Waveform Generation = OCnB OCRnB TCCRnA TCCRnB Related Links 5. Pin Configurations 5.2 Pin Descriptions 22.2.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... Table 22-1. Definitions Constant Description BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). 22.2.2 MAX The counter reaches its maximum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2A Register.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... Figure 22-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count clear TCNTn clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Table 22-2. Signal description (internal signals): Signal name Description count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero).
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... The following figure shows a block diagram of the output compare unit. Figure 22-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn =(8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn[1:0] COMnx[1:0] The OCR2x is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... 22.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the output compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform generation.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... The design of the output compare pin logic allows initialization of the OC2x state before the output is enabled. Note that some COM2x[1:0] bit settings are reserved for certain modes of operation. See Register Description. Related Links 19.7 Modes of Operation 22.6.1 Compare Output Mode and Waveform Generation The waveform generator uses the COM2x[1:0] bits differently in normal, CTC, and PWM modes.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... Figure 22-5. CTC Mode, Timing Diagram An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. Figure 22-6.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... 22.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM2[2:0] = 0x1 or 0x5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2[2:0] = 0x3, and OCR2A when MGM2[2:0] = 7.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... setting (or clearing) the OC2x register at compare match between OCR2x and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: �OCnxPCPWM = �clk_I/O � ⋅ 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... Figure 22-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn The following figure shows the setting of OCF2A in all modes except CTC mode. Figure 22-10.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... • • • • • • • • When switching between asynchronous and synchronous clocking of TC2, the registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is: 1. Disable the TC2 interrupts by clearing OCIE2x and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2x, and TCCR2x. 4. To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB. 5.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... • 22.10 rising TOSC1 edge. When waking up from Power-Save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-Save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: 1.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... 22.11.1 TC2 Control Register A Name: Offset: Reset: Property: Bit TCCR2A 0xB0 0x00 - 7 6 5 COM2A[1:0] Access Reset 4 3 2 1 COM2B[1:0] 0 WGM2[1:0] R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 7:6 – COM2A[1:0] Compare Output Mode for Channel A These bits control the Output Compare pin (OC2A) behavior.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... The table below shows the COM2A[1:0] bit functionality when the WGM2[2:0] bits are set to phase correct PWM mode. Table 22-5. Compare Output Mode, Phase Correct PWM Mode(1) COM2A[1] COM2A[0] Description 0 0 Normal port operation, OC2A disconnected. 0 1 WGM2[2 :0]: Normal port operation, OC2A disconnected. WGM2[2:1]: Toggle OC2A on compare match. 1 0 Clear OC2A on compare match when up-counting.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... COM2B[1] COM2B[0] Description 1 0 Clear OC0B on compare match, set OC0B at BOTTOM, (non-inverting mode) 1 1 Set OC0B on compare match, clear OC0B at BOTTOM, (inverting mode) Note: 1. A special case occurs when OCR2B equals TOP and COM2B[1] is set. In this case, the compare match is ignored, but the set or clear is done at TOP. Refer to 19.7.3 Fast PWM Mode for details.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... 1. 2. MAX = 0xFF BOTTOM = 0x00 © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... 22.11.2 TC2 Control Register B Name: Offset: Reset: Property: Bit Access Reset TCCR2B 0xB1 0x00 - 7 6 FOC2A FOC2B 5 4 WGM22 3 2 1 0 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 CS2[2:0] Bit 7 – FOC2A Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. To ensure compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... CS22 CS21 CS20 Description 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/32 (From prescaler) 1 0 0 clkI/O/64 (From prescaler) 1 0 1 clkI/O/128 (From prescaler) 1 1 0 clkI/O/256 (From prescaler) 1 1 1 clkI/O/1024 (From prescaler) If external pin modes are used for the timer/counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... 22.11.3 TC2 Counter Value Register Name: Offset: Reset: Property: Bit 7 TCNT2 0xB2 0x00 - 6 5 4 3 2 1 0 TCNT2[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – TCNT2[7:0] Timer/Counter 2 Counter Value The Timer/Counter register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... 22.11.4 TC2 Output Compare Register A Name: Offset: Reset: Property: Bit 7 OCR2A 0xB3 0x00 - 6 5 4 3 2 1 0 OCR2A[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR2A[7:0] Output Compare 2 A The output compare register A contains an 8-bit value that is continuously compared with the counter value (TCNT2).
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... 22.11.5 TC2 Output Compare Register B Name: Offset: Reset: Property: Bit 7 OCR2B 0xB4 0x00 - 6 5 4 3 2 1 0 OCR2B[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – OCR2B[7:0] Output Compare 2 B The output compare register B contains an 8-bit value that is continuously compared with the counter value (TCNT2).
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... 22.11.6 TC2 Interrupt Mask Register Name: Offset: Reset: Property: Bit 7 TIMSK2 0x70 0x00 - 6 5 4 3 Access Reset 2 1 0 OCIE2B OCIE2A TOIE2 R/W R/W R/W 0 0 0 Bit 2 – OCIE2B Timer/Counter 2, Output Compare B Match Interrupt Enable When the OCIE2B bit is written to '1' and the I-bit in the Status register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... 22.11.7 TC2 Interrupt Flag Register Name: Offset: Reset: Property: TIFR2 0x37 0x00 When addressing as I/O Register: address offset is 0x17 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... 22.11.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... If a write is performed to any of the five timer/counter2 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. Related Links 13.9 Timer/Counter Oscillator © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA 8-bit Timer/Counter2 (TC2) with PWM and A... 22.11.9 General Timer/Counter Control Register Name: Offset: Reset: Property: GTCCR 0x43 0x00 When addressing as I/O register: address offset is 0x23 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA Serial Peripheral Interface (SPI) 23. Serial Peripheral Interface (SPI) 23.1 Features • • • • • • • • 23.
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ATmega48PA/88PA/168PA Serial Peripheral Interface (SPI) Figure 23-1. SPI Block Diagram SPI2X SPI2X DIVIDER /2/4/8/16/32/64/128 Note: Refer to the pin-out description and the I/O Port description for SPI pin placement. The interconnection between master and slave CPUs with SPI is shown in the figure below. The system consists of two shift registers and a master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired slave.
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ATmega48PA/88PA/168PA Serial Peripheral Interface (SPI) an interrupt is requested. The slave may continue to place new data to be sent to SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer register for later use. Figure 23-2. SPI Master-Slave Interconnection SHIFT ENABLE The system is single buffered in the transmit direction and double buffered in the receive direction.
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ATmega48PA/88PA/168PA Serial Peripheral Interface (SPI) ret SPI_MasterTransmit: ; Start transmission of data (r16) out SPDR,r16 Wait_Transmit: ; Wait for transmission complete in r16, SPSR sbrs r16, SPIF rjmp Wait_Transmit ret C Code Example void SPI_MasterInit(void) { /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<
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ATmega48PA/88PA/168PA Serial Peripheral Interface (SPI) } return SPDR; Related Links 5.2 Pin Descriptions 25. USART in SPI (USARTSPI) Mode 14. Power Management and Sleep Modes 18. I/O-Ports 9. About Code Examples 23.3 SS Pin Functionality 23.3.1 Slave Mode When the SPI is configured as a slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs.
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ATmega48PA/88PA/168PA Serial Peripheral Interface (SPI) Table 23-2. SPI Modes SPI Mode Conditions Leading Edge Trailing Edge 0 CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 1 CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 2 CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 3 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) The SPI data transfer formats are shown in the following figure. Figure 23-3.
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ATmega48PA/88PA/168PA Serial Peripheral Interface (SPI) 23.5.1 SPI Control Register 0 Name: Offset: Reset: Property: SPCR0 0x4C [ID-000004d0] 0x00 When addressing as I/O register: address offset is 0x2C When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA Serial Peripheral Interface (SPI) Table 23-4. CPHA0 Functionality CPHA0 Leading Edge Trailing Edge 0 Sample Setup 1 Setup Sample Bits 1:0 – SPR0[1:0] SPI0 Clock Rate Select These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the table below. Table 23-5.
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ATmega48PA/88PA/168PA Serial Peripheral Interface (SPI) 23.5.2 SPI Status Register 0 Name: Offset: Reset: Property: SPSR0 0x4D [ID-000004d0] 0x00 When addressing as I/O Register: address offset is 0x2D When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA Serial Peripheral Interface (SPI) 23.5.3 SPI Data Register 0 Name: Offset: Reset: Property: SPDR0 0x4E [ID-000004d0] 0xXX When addressing as I/O Register: address offset is 0x2E When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... 24. Universal Synchronous Asynchronous Receiver Transceiver (USART) 24.1 Features • • • • • • • • • • • • 24.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... Figure 24-1.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... Figure 24-2. Clock Generation Logic, Block Diagram UBRRn U2Xn fosc Prescaling Down-Counter UBRRn+1 /2 /4 /2 0 1 0 OSC DDR_XCKn xcki XCKn Pin Sync Register Edge Detector 0 xcko DDR_XCKn 1 UMSELn 1 UCPOLn txclk 1 0 rxclk Signal description: 24.4.1 • • • txclk: Transmitter clock (internal signal). rxclk: Receiver base clock (internal signal). xcki: Input from XCKn pin (internal signal).
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... Note: 1. The baud rate is defined to be the transfer rate in bits per second (bps) BAUD Baud rate (in bits per second, bps) fOSC System oscillator clock frequency UBRRn Contents of the UBRRnH and UBRRnL registers, (0-4095). Some examples of UBRRn values for some system clock frequencies are found in Examples of Baud Rate Settings. 24.4.2 Double Speed Operation (U2Xn) The transfer rate can be doubled by setting the U2Xn bit in UCSRnA.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... The UCPOL bit UCRSC selects which XCKn clock edge is used for data sampling and which is used for data change. As the above timing diagram shows, when UCPOL is zero, the data will be changed at rising XCKn edge and sampled at falling XCKn edge. If UCPOL is set, the data will be changed at falling XCKn edge and sampled at rising XCKn edge. 24.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... �odd = �� − 1 ⊕ … ⊕ �3 ⊕ �2 ⊕ �1 ⊕ �0 ⊕ 1 Peven Parity bit using even parity Podd Parity bit using odd parity dn Data bit n of the character If used, the parity bit is located between the last data bit and first stop bit of a serial frame. 24.6 USART Initialization The USART has to be initialized before any communication can take place.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... } UCSR0C = (1<
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... The function simply waits for the transmit buffer to be empty by checking the UDRE flag, before loading it with new data to be transmitted. If the data register empty interrupt is utilized, the interrupt routine writes the data into the buffer. Related Links 9. About Code Examples 24.7.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... transmitted that has not yet been moved into the Shift register. For compatibility with future devices, always write this bit to zero when writing the UCSRnA register. When the Data Register Empty Interrupt Enable (UDRIE) bit in UCSRnB is written to '1', the USART data register empty interrupt will be executed as long as UDRE is set (provided that global interrupts are enabled). UDRE is cleared by writing UDRn.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ...
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ...
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... conditions and protocol handling. The FE flag is not affected by the setting of the USBS bit in UCSRnC since the receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. The DOR flag indicates data loss due to a receiver buffer full condition.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... } unsigned char dummy; while ( UCSR0A & (1<
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... Figure 24-6.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... • • • SF: First sample number used for majority voting. SF = 8 for normal speed and SF = 4 for Double Speed mode. SM: Middle sample number used for majority voting. SM = 9 for normal speed and SM = 5 for Double Speed mode. Rslow : is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... 24.10 Multi-Processor Communication Mode Setting the Multi-Processor Communication mode (MPCMn) bit in UCSRnA enables a filtering function of incoming frames received by the USART receiver. Frames that do not contain address information will be ignored and not put into the receive buffer.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... UBRRn values, which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table. Higher error ratings are acceptable, but the receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see also section Asynchronous Operational Range).
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... Baud Rate [bps] fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz U2Xn = 0 U2Xn = 0 U2Xn = 0 U2Xn = 1 U2Xn = 1 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... (1) UBRRn = 0, Error = 0.0% Table 24-7. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies Baud Rate [bps] fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz U2Xn = 0 U2Xn = 0 U2Xn = 0 U2Xn = 1 U2Xn = 1 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... 24.12.1 USART I/O Data Register 0 Name: Offset: Reset: Property: UDR0 0xC6 0x00 - The USART transmit data buffer register and USART receive data buffer registers share the same I/O address referred to as USART Data Register (UDR0). The Transmit Data Buffer register (TXB) will be the destination for data written to the UDR0 location. Reading the UDR0 location will return the contents of the Receive Data Buffer register (RXB).
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... 24.12.2 USART Control and Status Register 0 A Name: Offset: Reset: Property: Bit UCSR0A 0xC0 0x20 - 7 6 5 4 3 2 1 0 RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 Access R R/W R R R R R/W R/W Reset 0 0 1 0 0 0 0 0 Bit 7 – RXC0 USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data).
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... This bit is reserved in MSPIM. Bit 1 – U2X0 Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. This bit is reserved in MSPIM.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... 24.12.3 USART Control and Status Register 0 B Name: Offset: Reset: Property: Bit Access Reset UCSR0B 0xC1 0x00 - 7 6 5 4 3 2 1 0 RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 R/W R/W R/W R/W R/W R/W R R/W 0 0 0 0 0 0 0 0 Bit 7 – RXCIE0 RX Complete Interrupt Enable 0 Writing this bit to one enables interrupt on the RXC0 flag.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... Bit 0 – TXB80 Transmit Data Bit 8 0 TXB80 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDR0. This bit is reserved in MSPIM. © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... 24.12.4 USART Control and Status Register 0 C Name: Offset: Reset: Property: Bit UCSR0C 0xC2 0x06 - 7 6 5 UMSEL0 [1:0] Access Reset 4 UPM0 [1:0] 3 2 1 0 USBS0 UCSZ01 / UCSZ00 / UCPOL0 UDORD0 UCPHA0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 1 1 0 Bits 7:6 – UMSEL0 [1:0] USART Mode Select 0 These bits select the mode of operation of the USART0 Table 24-8.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... Table 24-10. Stop Bit Settings USBS0 Stop Bit(s) 0 1-bit 1 2-bit This bit is reserved in Master SPI Mode (MSPIM). Bit 2 – UCSZ01 / UDORD0 USART Character Size / Data Order UCSZ0[1:0]: USART Modes: The UCSZ0[1:0] bits combined with the UCSZ02 bit in UCSR0B sets the number of data bits (Character Size) in a frame the receiver and transmitter use. Table 24-11.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... Master SPI Mode: The UCPOL0 bit sets the polarity of the XCK0 clock. The combination of the UCPOL0 and UCPHA0 bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and Timing for details. © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Universal Synchronous Asynchronous Receiver ... 24.12.5 USART Baud Rate 0 Register Low and High byte Name: Offset: Reset: Property: UBRR0L and UBRR0H 0xC4 0x00 - The UBRR0L and UBRR0H register pair represents the 16-bit value, UBRR0. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega48PA/88PA/168PA USART in SPI (USARTSPI) Mode 25. USART in SPI (USARTSPI) Mode 25.1 Features 25.
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ATmega48PA/88PA/168PA USART in SPI (USARTSPI) Mode 25.4 BAUD Baud rate (in bits per second, bps) fOSC System oscillator clock frequency UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095) SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in the following figure.
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ATmega48PA/88PA/168PA USART in SPI (USARTSPI) Mode A frame starts with the least or most significant data bit. Then the next data bits, up to a total of eight, are succeeding, ending with the most or least significant bit accordingly. When a complete frame is transmitted, a new frame can directly follow it, or the communication line can be set to an idle (high) state. The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The receiver and transmitter use the same setting.
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ATmega48PA/88PA/168PA USART in SPI (USARTSPI) Mode /* Setting the XCKn port pin as output, enables master mode. */ XCKn_DDR |= (1<
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ATmega48PA/88PA/168PA USART in SPI (USARTSPI) Mode in r16, UDRn ret Example 25-4. C Code Example { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
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ATmega48PA/88PA/168PA USART in SPI (USARTSPI) Mode Table 25-3. Comparison of USART in MSPIM Mode and SPI Pins 25.8 USART_MSPIM SPI Comments TxDn MOSI Master Out only RxDn MISO Master In only XCKn SCK (Functionally identical) (N/A) SS Not supported by USART in MSPIM Register Description Refer to the USART register description. Related Links 24.12 Register Description © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) 26. Two-Wire Serial Interface (TWI) 26.1 Features • • • • • • • • • • • 26.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Table 26-1. TWI Terminology Term Description Master The device that initiates and terminates a transmission. The master also generates the SCL clock. Slave The device addressed by a master. Transmitter The device placing data on the bus. Receiver The device reading data from the bus. This device has one instance of TWI. For this reason, the instance index n is omitted. The Power Reduction TWI bit in the Power Reduction Register (PRRn.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) 26.3.2 START and STOP Conditions The master initiates and terminates a data transmission. The transmission is initiated when the master issues a START condition on the bus, and it is terminated when the master issues a STOP condition. Between a START and a STOP condition, the bus is considered busy, and no other master should try to seize control of the bus. A special case occurs when a new START condition is issued between a START and STOP condition.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Figure 26-4. Address Packet Format Addr MSB Addr LSB R/W ACK 7 8 9 SDA SCL 1 2 START 26.3.4 Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the ,master generates the clock and the START and STOP conditions, while the receiver is responsible for acknowledging the reception.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Figure 26-6. Typical Data Transmission Addr MSB Addr LSB R/W ACK Data MSB 7 8 9 1 Data LSB ACK 8 9 SDA SCL 1 2 START 26.4 SLA+R/W 2 7 Data Byte STOP Multi-Master Bus Systems, Arbitration, and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Figure 26-7. SCL Synchronization Between Multiple Masters TA low TA high SCL from Master A TBlow TBhigh SCL from Master B SCL Bus Line Masters Start Counting Low Period Masters Start Counting High Period Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the master had output, it has lost the arbitration.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In other words; All transmissions must contain the same number of data packets, otherwise, the result of the arbitration is undefined. 26.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) 26.5.2 Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBRn) and the Prescaler bits in the TWI Status Register (TWSRn). Slave operation does not depend on bit rate or prescaler settings, but the CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) is updated with a status code identifying the event. The TWSRn only contains relevant status information when the TWI interrupt flag is asserted. At all other times, the TWSRn contains a special status code indicating that no relevant status information is available. As long as the TWINT flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Application Action Figure 26-10. Interfacing the Application to the TWI in a Typical Transmission 1. Application writes to TWCR to initiate transmission of START TWI Hardware Action TWI bus 1. 2. 3. 4. 5. 3. Check TWSR to see if START was sent. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, making sure that TWINT is written to one, and TWSTA is written to zero. START 2.TWINT set.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) 6. 7. When the data packet has been transmitted, the TWINT flag in TWCRn is set and TWSRn is updated with a status code indicating that the data packet has successfully been sent. The status code will also reflect whether a slave acknowledged the packet or not. The application software should now examine the value of TWSRn, to make sure that the data packet was successfully transmitted, and that the value of the ACK bit was as expected.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Assembly Code Example 4 5 6 7 C Example Comments wait2: in r16,TWCR0 sbrs r16,TWINT rjmp wait2 while (!(TWCR0 & (1<
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) W Write bit (low level at SDA) A Acknowledge bit (low level at SDA) A Not acknowledge bit (high level at SDA) Data 8-bit data byte P STOP condition SLA Slave Address Circles are used to indicate that the TWINT flag is set. The numbers in the circles show the status code held in TWSRn, with the prescaler bits masked to zero. At these points, actions must be taken by the application to continue or complete the TWI transfer.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) must be transmitted. This is done by writing SLA+W to the TWI Data Register (TWDRn). Thereafter, the TWCRn.TWINT flag should be cleared (by writing a '1' to it) to continue the transfer. This is accomplished by writing a value to TWRC of the type TWCR=1x00x10x. When SLA+W has been transmitted and an acknowledgment bit has been received, TWINT is set again and a number of status codes in TWSR are possible.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Status Code (TWSR) Prescaler Bits are 0 Status of the Two-Wire Serial Bus and Two-Wire Serial Interface Hardware Application Software Response To/From TWDR Next Action Taken by TWI Hardware To TWCRn STA STO TWINT TWEA transmitted and TWSTO Flag will be reset 0x20 0x28 0x30 SLA+W has been transmitted; Load data NOT ACK has been received byte or 0 0 1 X Data byte will be transmitted and ACK or NOT ACK will be received No TWDR action or 1 0
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Status Code (TWSR) Prescaler Bits are 0 0x38 Status of the Two-Wire Serial Bus and Two-Wire Serial Interface Hardware Arbitration lost in SLA+W or data bytes © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Figure 26-12.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Figure 26-13. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER ........ Device 3 Device n R1 R2 SDA SCL A START condition is sent by writing to the TWI Control Register (TWCRn) a value of the type TWCRn=1x10x10x: • TWCRn.TWEN must be written to '1' to enable the two-wire serial interface • TWCRn.TWSTA must be written to '1' to transmit a START condition • TWCRn.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Status Code (TWSRn) Status of the Two-Wire Serial Application Software Response Next Action Taken by TWI Bus and Two-Wire Serial Hardware To/From To TWCRn Interface Hardware Prescaler Bits TWD STA STO TWINT TWEA are 0 ACK or NOT ACK will be received 0x10 A repeated START condition has been transmitted Load SLA+R 0 0 1 X SLA+R will be transmitted ACK or NOT ACK will be received Load SLA+W 0 0 1 X SLA+W will be transmitted Logic will switch to
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Figure 26-14.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Figure 26-15. Data Transfer in Slave Transmitter Mode VCC Device 1 Device 2 SLA VE TRANSMITTER MASTER RECEIVER Device 3 ........ Device n R1 R2 SDA SCL To initiate the SR mode, the TWI (Slave) Address Register (TWARn) and the TWI Control Register (TWCRn) must be initialized as follows: The upper seven bits of TWARn are the address to which the two-wire serial interface will respond when addressed by a master (TWARn.TWA[6:0]).
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Note: The Two-wire serial interface Data Register (TWDRn) does not reflect the last byte present on the bus when waking up from these Sleep modes. Table 26-5.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Status Code (TWSRb) Prescaler Bits are 0 0xC8 Status of the Two-Wire Serial Application SofTWARne Response Next Action Taken by TWI Bus and Two-Wire Serial Hardware To/From To TWCRn Interface Hardware TWDRn STA STO TWINT TWEA Last data byte in TWDRn has been transmitted (TWEA = “0”); No TWDRn action 0 0 1 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA 0 0 1 1 Switched to the not addressed Slave mode; ACK has bee
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Figure 26-16. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A A DATA 0xA8 Arbitration lost as master and addressed as slave A DATA P or S 0xC0 0xB8 A 0xB0 Last data byte transmitted. Switched to not addressed slave (TWEA = '0') A All 1's P or S 0xC8 From master to slave DATA From slave to master 26.7.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) TWCRn must hold a value of the type TWCRn=0100010x - TWCRn.TWEN must be written to '1' to enable the TWI. TWCRn.TWEA bit must be written to '1' to enable the acknowledgment of the device’s own slave address or the general call address. TWCRn.TWSTA and TWSTO must be written to zero.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Status Code Status of the Two-Wire Serial (TWSR) Bus and Two-Wire Serial Interface Hardware Prescaler Bits are 0 Application SofTWARne Response To/from TWDRn General call address has been received; To TWCRn Next Action Taken by TWI Hardware STA STO TWINT TWEA X 0 1 1 Data byte will be received and ACK will be returned X 0 1 0 Data byte will be received and NOT ACK will be returned X 0 1 1 Data byte will be received and ACK will be retu
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Status Code Status of the Two-Wire Serial (TWSR) Bus and Two-Wire Serial Interface Hardware Prescaler Bits are 0 Application SofTWARne Response To/from TWDRn NOT ACK has been returned To TWCRn Next Action Taken by TWI Hardware STA STO TWINT TWEA 0 0 1 1 Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1” 1 0 1 0 Switched to the not addressed Slave mode; no recognition of own SLA or GCA
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Status Code Status of the Two-Wire Serial (TWSR) Bus and Two-Wire Serial Interface Hardware Prescaler Bits are 0 Application SofTWARne Response To/from TWDRn Next Action Taken by TWI Hardware To TWCRn STA STO TWINT TWEA GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free Figure 26-18. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Status 0xF8 indicates that no relevant information is available because the TWINT flag is not set. This occurs between other states, and when the TWI is not involved in a serial transfer. Status 0x00 indicates that a bus error has occurred during a two-wire serial bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) Figure 26-19. Combining Several TWI Modes to Access a Serial EEPROM Master Transmitter S SLA+W A ADDRESS Master Receiver A S = START Rs A DATA Rs = REPEATED START Transmitted from master to slave 26.8 SLA+R A P P = STOP Transmitted from slave to master Multi-Master Systems and Arbitration If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more of them.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) This is summarized in the next figure. Possible status values are given in circles. Figure 26-21. Possible Status Codes Caused by Arbitration START SLA Data Arbitration lost in SLA Own Address / General Call received No STOP Arbitration lost in Data 38 TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free Yes Direction Write 68/78 Read B0 26.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) 26.9.1 TWI Bit Rate Register Name: Offset: Reset: Property: Bit 7 TWBR 0xB8 0x00 - 6 5 4 3 2 1 0 TWBR [7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – TWBR [7:0] TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) 26.9.2 TWI Status Register Name: Offset: Reset: Property: Bit TWSR 0xB9 0xF8 - 7 6 5 4 3 TWS7 TWS6 TWS5 TWS4 TWS3 2 1 0 Access R R R R R R R/W R/W Reset 1 1 1 1 1 0 0 0 TWPS[1:0] Bits 3, 4, 5, 6, 7 – TWS TWI Status Bit The TWS[7:3] reflect the status of the TWI logic and the 2-wire serial bus. The different status codes are described later in this section.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) 26.9.3 TWI (Slave) Address Register Name: Offset: Reset: Property: TWAR 0xBA 0xFE - The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the Master modes. In multi master systems, TWAR must be set in masters which can be addressed as slaves by other masters.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) 26.9.4 TWI Data Register Name: Offset: Reset: Property: TWDR 0xBB 0xFF - In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt flag (TWINT) is set by hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) 26.9.5 TWI Control Register Name: Offset: Reset: Property: TWCR 0xBC 0x00 - The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) STOP condition, but the TWI returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state. Bit 3 – TWWC TWI Write Collision Flag The TWWC bit is set when attempting to write to the TWDR when TWINT is low. This flag is cleared by writing the TWDR when TWINT is high. Bit 2 – TWEN TWI Enable The TWEN bit enables TWI operation and activates the TWI interface.
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ATmega48PA/88PA/168PA Two-Wire Serial Interface (TWI) 26.9.6 TWI (Slave) Address Mask Register Name: Offset: Reset: Property: Bit Access Reset TWAMR 0xBD 0x00 - 7 6 5 4 3 2 1 TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 0 R/W R/W R/W R/W R/W R/W R/W R 0 0 0 0 0 0 0 0 Bits 1, 2, 3, 4, 5, 6, 7 – TWAM TWI (Slave) Address The TWAMR can be loaded with a 7-bit slave address mask.
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ATmega48PA/88PA/168PA Analog Comparator (AC) 27. Analog Comparator (AC) 27.1 Overview The analog comparator evaluates the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output (ACO) is set. The comparator’s output can be set to trigger the timer/counter1 input capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the analog comparator.
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ATmega48PA/88PA/168PA Analog Comparator (AC) Table 27-1. Analog Comparator Multiplexed Input 27.3 ACME ADEN MUX[2:0] Analog Comparator Negative Input 0 x xxx AIN1 1 1 xxx AIN1 1 0 000 ADC0 1 0 001 ADC1 1 0 010 ADC2 1 0 011 ADC3 1 0 100 ADC4 1 0 101 ADC5 1 0 110 ADC6 1 0 111 ADC7 Register Description © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Analog Comparator (AC) 27.3.1 Analog Comparator Control and Status Register Name: Offset: Reset: Property: ACSR 0x50 N/A When addressing as I/O Register: address offset is 0x30 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA Analog Comparator (AC) Bits 1:0 – ACIS[1:0] Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the analog comparator interrupt. Table 27-2. ACIS[1:0] Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator interrupt on output toggle. 0 1 Reserved 1 0 Comparator interrupt on falling output edge. 1 1 Comparator interrupt on rising output edge.
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ATmega48PA/88PA/168PA Analog Comparator (AC) 27.3.2 Digital Input Disable Register 1 Name: Offset: Reset: Property: Bit 7 DIDR1 0x7F 0x00 - 6 5 4 3 2 1 0 AIN1D AIN0D Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 0, 1 – AIND AIN Digital Input Disable When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) 28. Analog-to-Digital Converter (ADC) 28.1 Features • • • • • • • • • • • • • • 28.2 10-bit Resolution 0.5 LSB Integral Non-Linearity ±2 LSB Absolute Accuracy 13 - 260 μs Conversion Time Up to 76.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) Figure 28-1. Analog-to-Digital Converter Block Schematic Operation ADC CONVERSION COMPLETE IRQ 15 ADC[9:0] ADPS1 ADPS0 ADPS2 ADIF ADFR ADEN ADSC 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL. & STATUS REGISTER (ADCSRA) MUX0 MUX2 MUX1 MUX3 ADLAR REFS0 REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS MUX DECODER CHANNEL SELECTION PRESCALER AVCC CONVERSION LOGIC INTERNAL 1.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) to the same conversion: Once ADCL is read, the ADC access to the data registers is blocked. This means that if ADCL has been read, and a second conversion completes before ADCH is read, neither register is updated and the result from the second conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) and updating the ADC data register. The first conversion must be started by writing a '1' to ADCSRA.ADSC. In this mode, the ADC will perform successive conversions independently of whether the ADC Interrupt Flag (ADIF) is cleared or not. If Auto triggering is enabled, single conversions can be started by writing ADCSRA.ADSC to '1'. ADSC can also be used to determine if a conversion is in progress.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) When auto triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) Figure 28-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Prescaler Reset Sample & Hold Prescaler Reset Conversion Complete MUX and REFS Update Figure 28-7.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (indicated by ADCSRA.ADIF set).
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. 28.6 ADC Noise Canceler The ADC features a noise canceler that enables conversion during Sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: 1. 2.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 1.1.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) Note: If the resistivity in the inductor is too high, the AVCC may exceed its range, VCC - 0.3V < AVCC < VCC + 0.3V. 28.6.3 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) Figure 28-12. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF • Input Voltage Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 28-13. Differential Non-Linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 • • 28.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) where VIN is the voltage on the selected input pin, and VREF the selected voltage reference (see also descriptions of ADMUX.REFSn and ADMUX.MUX). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB. 28.8 Temperature Measurement The temperature measurement is based on an on-chip temperature sensor that is coupled to a single ended temperature sensor channel.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) 28.9.1 ADC Multiplexer Selection Register Name: Offset: Reset: Property: Bit ADMUX 0x7C 0x00 - 7 6 REFS[1:0] Access Reset 5 4 3 2 ADLAR 1 0 MUX[3:0] R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Bits 7:6 – REFS[1:0] Reference Selection These bits select the voltage reference for the ADC. If these bits are changed during a conversion, the change will not go into effect until this conversion is complete (ADIF in ADCSRA is set).
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) MUX[3:0] Single Ended Input 0101 ADC5 0110 ADC6 0111 ADC7 1000 Temperature sensor 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 1.1V (VBG) 1111 0V (GND) Related Links 28.9.3 ADCL and ADCH (ADLAR = 0) © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) 28.9.2 ADC Control and Status Register A Name: Offset: Reset: Property: Bit Access Reset ADCSRA 0x7A 0x00 - 7 6 5 4 3 ADEN ADSC ADATE ADIF ADIE 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 ADPS[2:0] Bit 7 – ADEN ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) Table 28-5. Input Channel Selection ADPS[2:0] Division Factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128 © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) 28.9.3 ADC Data Register Low and High Byte (ADLAR=0) Name: Offset: Reset: ADCL and ADCH (ADLAR = 0) 0x78 0x00 The ADCL and ADCH register pair represents the 16-bit value, ADC data register. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) 28.9.4 ADC Data Register Low and High Byte (ADLAR=1) Name: Offset: Reset: ADCL and ADCH (ADLAR = 1) 0x78 0x00 The ADCL and ADCH register pair represents the 16-bit value, ADC data register. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) 28.9.5 ADC Control and Status Register B Name: Offset: Reset: Property: Bit ADCSRB 0x7B 0x00 - 7 6 5 4 3 2 ACME Access 1 0 ADTS[2:0] R/W R/W R/W R/W 0 0 0 0 Reset Bit 6 – ACME Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the analog comparator.
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ATmega48PA/88PA/168PA Analog-to-Digital Converter (ADC) 28.9.6 Digital Input Disable Register 0 Name: Offset: Reset: Property: DIDR0 0x7E 0x00 - When the respective bits are written to logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7...
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ATmega48PA/88PA/168PA debugWIRE On-chip Debug System 29. debugWIRE On-chip Debug System 29.1 Features • • • • • • • • • • 29.
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ATmega48PA/88PA/168PA debugWIRE On-chip Debug System When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • • • • 29.4 Pull-up resistors on the dW/(RESET) line must not be smaller than 10 kΩ. The pull-up resistor is not required for debugWIRE functionality. Connecting the RESET pin directly to VCC will not work. Capacitors connected to the RESET pin must be disconnected when using debugWire. All external reset sources must be disconnected.
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ATmega48PA/88PA/168PA debugWIRE On-chip Debug System 29.6.1 debugWire Data Register Name: Offset: Reset: Property: DWDR 0x51 [ID-000004d0] 0x00 When addressing as I/O register: address offset is 0x31 When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
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ATmega48PA/88PA/168PA Self-Programming the Flash 30. Self-Programming the Flash 30.1 Overview In ATmega48PA, there is no Read-While-Write support and no separate boot loader section. The SPM instruction can be executed from the entire Flash. The device provides a self-programming mechanism for downloading and uploading program code by the MCU itself. The self-programming can use any available data interface and associated protocol to read code and write (program) that code into the program memory.
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ATmega48PA/88PA/168PA Self-Programming the Flash buffer will auto-erase after a page write operation or by writing the RWWSRE bit in SPMCSR. It is also erased after a system Reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM page load operation, all data loaded will be lost. 30.1.
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ATmega48PA/88PA/168PA Self-Programming the Flash Figure 30-1. Addressing the Flash During SPM BIT 15 ZPAGEMSB ZPCMSB 1 0 0 Z - REGISTER PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: The different variables used in this figure are listed in page size section in memory programming chapter. Related Links 32.6 Page Size 30.2.
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ATmega48PA/88PA/168PA Self-Programming the Flash The algorithm for reading the Fuse Low byte (FLB) is similar to the one described above for reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR (SPMCSR.BLBSET and SPMCSR.SPMEN). When an LPM instruction is executed within three cycles after the SPMCSR.BLBSET and SPMCSR.SPMEN are set, the value of the Fuse Low byte (FLB) will be loaded in the destination register as shown below.
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ATmega48PA/88PA/168PA Self-Programming the Flash 30.2.4 Programming Time for Flash when Using SPM The calibrated RC oscillator is used to time Flash accesses. The following table shows the typical programming time for Flash accesses from the CPU. Table 30-1. SPM Programming Time Symbol Min. Programming Time Max Programming Time Flash write (Page erase, page write, and write Lock bits by SPM) 3.2ms 3.4ms Note: Minimum and maximum programming time is per individual operation. 30.2.
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ATmega48PA/88PA/168PA Self-Programming the Flash Wrloop: ld r0, Y+ ld r1, Y+ ldi spmcrval, (1<
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ATmega48PA/88PA/168PA Self-Programming the Flash ; re-enable the RWW section ldi spmcrval, (1<
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ATmega48PA/88PA/168PA Self-Programming the Flash 30.3.1 Store Program Memory Control and Status Register Name: Offset: Reset: Property: SPMCSR 0x57 [ID-000004d0] 0x00 When addressing I/O registers as data space the offset address is 0x37 The Store Program Memory Control and Status register contains the control bits needed to control the program memory operations. When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used.
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ATmega48PA/88PA/168PA Self-Programming the Flash Bit 1 – PGERS Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... 31. Boot Loader Support – Read-While-Write Self-programming (BTLDR) 31.1 Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 1. A page is a section in the Flash consisting of several bytes (see Table. No.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... 31.4 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write (RWW) or if the CPU is halted during a boot loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ fuses as described above, the Flash is also divided into two fixed sections; the RWW section and the No Read-While-Write (NRWW) section.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... Figure 31-1. Read-While-Write vs. No Read-While-Write Read-While-Write (RWW) Section Z-pointer Addresses RWW Section Z-pointer Addresses NRWW Section No Read-While-Write (NRWW) Section CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... Figure 31-2. Memory Sections Related Links 31.8.15 ATmega168PA Boot Loader Parameters 31.8.14 ATmega88PA Boot Loader Parameters 31.5 Boot Loader Lock Bits If no boot loader capability is needed, the entire Flash is available for application code. The boot loader has two separate sets of boot lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... • • • • To protect the entire Flash from a software update by the MCU To protect only the boot loader Flash section from a software update by the MCU To protect only the application Flash section from a software update by the MCU Allow software update in the entire Flash The boot lock bits can be set in software and in Serial or Parallel Programming mode, but they can be cleared by a chip erase command only.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... 31.6 Entering the Boot Loader Program Entering the boot loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via USART or SPI interface. Alternatively, the boot Reset fuse can be programmed so that the Reset vector is pointing to the boot Flash start address after a reset. In this case, the boot loader is started after a Reset.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... Figure 31-3. Addressing the Flash During SPM BIT 15 ZPAGEMSB ZPCMSB 1 0 0 Z - REGISTER PROGRAM COUNTER PCMSB PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: The different variables used in this figure are listed in the Related Links. Related Links 32.6 Page Size 31.8.14 ATmega88PA Boot Loader Parameters 31.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. When using Alternative 1, the boot loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... software itself, it is recommended to program the Boot Lock bit11 to protect the boot loader software from any internal software changes. 31.8.6 Prevent Reading the RWW Section During Self-Programming During self-programming (either page erase or page write), the RWW section is always blocked for reading. The user software itself must prevent that this section is addressed during the self-programming operation.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... bits in SPMCSR (SPMCSR.BLBSET and SPMCSR.SPMEN). When an LPM instruction is executed within three cycles after the SPMCSR.BLBSET and SPMCSR.SPMEN are set, the value of the Fuse Low byte (FLB) will be loaded into the destination register as shown below. Bit 7 6 5 4 3 2 1 0 Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0 Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... 3. while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. Keep the AVR core in Power-Down Sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR register and thus the Flash from unintentional writes. 31.8.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-...
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-...
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... Table 31-6.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... Z0: should be zero for all SPM commands, byte select for the LPM instruction. Please refer to 31.7 Addressing the Flash During Self-Programming for details about the use of Z-pointer during Self-Programming. 31.8.15 ATmega168PA Boot Loader Parameters The following tables are the parameters used in the description of the self programming are given. Table 31-9.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... Variable Corresponding Description Z-value(1) ZPAGEMSB Z6 Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not used, the ZPAGEMSB equals PAGEMSB + 1. PCPAGE PC[12:6] Z13:Z7 Program counter page address: Page select, for page erase and page write PCWORD PC[5:0] Program counter word address: Word select, for filling temporary buffer (must be zero during page write operation) Z6:Z1 Note: 1.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... 31.9.1 Store Program Memory Control and Status Register (SPMCSR) Name: Offset: Reset: Property: SPMCSR 0x57 [ID-000004d0] 0x00 When addressing as I/O register: address offset is 0x37 The Store Program Memory Control and Status Register (SPMCSR) contains the control bits needed to control the boot loader operations. When addressing I/O registers as data space using LD and ST instructions, the provided offset must be used.
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ATmega48PA/88PA/168PA Boot Loader Support – Read-While-Write Self-... the Z-pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR register (SPMCSR.BLBSET and SPMCSR.SPMEN), will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) 32. Memory Programming (MEMPROG) 32.1 Program And Data Memory Lock Bits The device provides six Lock bits. These can be left unprogrammed ('1') or can be programmed ('0') to obtain the additional features listed in the table Lock Bit Protection Modes below. The Lock bits can only be erased to '1' with the Chip Erase command. Table 32-1. Lock Bit Byte(1) Lock Bit Byte Bit No.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) Table 32-3. Lock Bit Protection - BLB0 Mode(1)(2) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or Load Program Memory (LPM) instruction accessing the application section. 2 1 0 SPM is not allowed to write to the application section. 3 0 0 SPM is not allowed to write to the application section, and LPM executing from the boot loader section is not allowed to read from the application section.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) Table 32-5. Extended Fuse Byte for ATmega48PA Extended Fuse Byte Bit No. Description Default Value – 7 – 1 – 6 – 1 – 5 – 1 – 4 – 1 – 3 – 1 – 2 – 1 (unprogrammed) – 1 – 1 (unprogrammed) SELFPRGEN 0 Self Programming Enable 1 (unprogrammed) Table 32-6. Extended Fuse Byte for ATmega88PA/ATmega168PA Extended Fuse Byte Bit No.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) High Fuse Byte Bit No. Description Default Value BODLEVEL1(4) 1 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL0(4) 0 Brown-out Detector trigger level 1 (unprogrammed) Note: 1. Refer to Alternate Functions of Port C in I/O-Ports chapter for description of RSTDISBL Fuse. 2. The SPIEN Fuse is not accessible in serial programming mode. 3. Refer to WDTCSR – Watchdog Timer Control Register for details. 4.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) 13.11 System Clock Prescaler 32.2.1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE fuse, which will take effect once it is programmed. The fuses are also latched on power-up in Normal mode. 32.3 Signature Bytes The device have a three-byte signature code.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) 32.6 Page Size Table 32-10. No. of Words in a Page and No. of Pages in the Flash Device Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB ATmega48PA 2K words (4 KB) 32 words PC[4:0] 64 PC[10:5] 10 ATmega88PA 4K words (8 KB) 32 words PC[4:0] 128 PC[11:5] 11 ATmega168PA 8K words (16 KB) 64 words PC[5:0] 128 PC[12:6] 12 Table 32-11. No. of Words in a Page and No. of Pages in the EEPROM 32.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) Figure 32-1. Parallel Programming +4.5 - 5.5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 +12V BS2 VCC +4.5 - 5.5V AVCC PC[1:0]:PB[5:0] DATA RESET PC2 XTAL1 GND Note: VCC - 0.3V < AVCC < VCC + 0.3V; however, AVCC should always be within 4.5 - 5.5V Table 32-12.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) Pin Symbol Value XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 32-14. XA1 and XA0 Coding XA1 XA0 Action When XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1) 0 1 Load Data (High or Low data byte for Flash determined by BS1) 1 0 Load Command 1 1 No Action, Idle Table 32-15.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) 1. 2. 3. 4. 5. 6. 32.8.2 Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. • • • 32.8.3 Set the Prog_enable pins listed in the table Pin Values Used to Enter Programming Mode above to “0000”, RESET pin to 0V and VCC to 0V. Apply 4.5–5.5V between VCC and GND. Monitor VCC, and as soon as VCC reaches 0.9–1.1V, apply 11.5–12.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) 2. 3. 4. Set BS1 to “0”. This selects low address. Set DATA = Address low byte (0x00 - 0xFF). Give XTAL1 a positive pulse. This loads the address low byte. Step C. Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. Step D. Load Data High Byte 1. Set BS1 to “1”. This selects high data byte. 2. Set XA1, XA0 to “01”.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are Reset. Figure 32-2. Addressing the Flash Which is Organized in Pages PROGRAM COUNTER PCMSB PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: PCPAGE and PCWORD are listed in table No. of Words in a Page and No.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) algorithm for the EEPROM data memory is as follows (for details on Command, Address, and Data loading, refer to 32.8.4 Programming the Flash): 1. 2. 3. 4. 5. 6. 7. Step A: Load Command “0001 0001”. Step G: Load Address High Byte (0x00 - 0xFF). Step B: Load Address Low Byte (0x00 - 0xFF). Step C: Load Data (0x00 - 0xFF). Step E: Latch data (give PAGEL a positive pulse). Step K: Repeat 3 through 5 until the entire buffer is filled.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) 1. 2. 3. 4. 5. 32.8.8 Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to 32.8.4 Programming the Flash for details on Command and Data loading): 1. 2. 3. 32.8.9 Step A: Load Command “0000 0011”. Step G: Load Address High Byte (0x00 - 0xFF). Step B: Load Address Low Byte (0x00 - 0xFF). Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. Set OE to “1”.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) Figure 32-4. Programming the FUSES Waveforms Write Fuse Low byte A DATA 0x40 A C DATA XX Write Extended Fuse byte Write Fuse high byte 0x40 A C DATA XX 0x40 C DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 32.8.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to 32.8.4 Programming the Flash for details on command and data loading): 1. 2. 3. Step A: Load Command “0010 0000”.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) Figure 32-5. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read 0 Fuse Low Byte 0 Extended Fuse Byte 1 DATA BS2 0 Lock Bits 1 Fuse High Byte 1 BS1 BS2 32.8.13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to 32.8.4 Programming the Flash for details on command and address loading): 1. 2. 3. 4. Step A: Load Command “0000 1000”. Step B: Load Address Low Byte (0x00 - 0x02).
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) Figure 32-6. Serial Programming and Verify, VCC = 1.8 - 5.5V +1.8 - 5.5V VCC MOSI PB5 MISO PB6 SCK PB7 +1.8 - 5.5V (2) AVCC XTAL1 RESET GND Note: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within the specified voltage range (VCC) for the device.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) 32.9.2 Serial Programming Algorithm When writing serial data to the device, data is clocked on the rising edge of SCK. When reading data from the device, data is clocked on the falling edge of SCK. Please refer to the figure, serial programming waveforms in SPI serial programming characteristics section for timing details.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) Table 32-17. Typical Wait Delay Before Writing the Next Flash or EEPROM Location 32.9.3 Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 3.6 ms tWD_ERASE 10.5 ms tWD_FUSE 4.5 ms Serial Programming Instruction Set This section describes the instruction set. Table 32-18.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) 1. 2. 3. 4. 5. 6. Not all instructions are applicable for all parts. a = address. Bits are programmed ‘0’, unprogrammed ‘1’. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’). Refer to the corresponding section for Fuse and Lock bits, Calibration and Signature bytes and page size. Instructions accessing program memory use a word address. This address may be random within the page range. Note: See http://www.microchip.
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ATmega48PA/88PA/168PA Memory Programming (MEMPROG) 32.9.4 SPI Serial Programming Characteristics Figure 32-8. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Electrical Characteristics 33. Electrical Characteristics 33.1 Absolute Maximum Ratings Table 33-1. Absolute Maximum Ratings Operating Temperature -55°C to +125°C Storage Temperature -65°C to +150°C Voltage on any Pin except RESET with respect to Ground -0.5V to VCC+0.5V Voltage on RESET with respect to Ground -0.5V to +13.0V Maximum Operating Voltage 6.0V DC Current per I/O Pin 40.0mA DC Current VCC and GND Pins 200.
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ATmega48PA/88PA/168PA Electrical Characteristics Symbol Parameter Condition Min. VIH3 VCC = 1.8V - 2.4V 0.7VCC(2) VCC + 0.5 V VCC = 2.4V - 5.5V 0.6VCC(2) VCC + 0.5 VOL Input High Voltage, RESET pin as I/O Output Low Voltage(4) except RESET pin IOL = 20mA, VCC = 5V IOL = 10mA, VCC = 3V VOH Output High Voltage(3) except Reset pin Typ. Max. Units TA=85°C 0.9 V TA=105°C 1.0 V TA=85°C 0.6 V TA=105°C 0.7 V IOH = -20mA, TA=85°C 4.2 TA=105°C 4.1 VCC = 5V V IOH = -10mA, TA=85°C 2.
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ATmega48PA/88PA/168PA Electrical Characteristics 4. If IIOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 4.1. The sum of all IOL, for ports C0 - C5, ADC7, ADC6 should not exceed 100mA. 4.2.
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ATmega48PA/88PA/168PA Electrical Characteristics 1. 2. 3. Values with Minimizing Power Consumption enabled (0xFF). Typical values at 25°C. Maximum values are test limits in production. The current consumption values include input leakage current. 33.2.2 ATmega88PA DC Characteristics – Current Consumption Table 33-4. DC characteristics - TA = -40°C to 85/105°C, VCC = 1.8V to 5.5V (unless otherwise noted) Typ.(2) Max. Units T = 85°C 0.2 0.5 mA T = 105°C 0.2 0.6 T = 85°C 1.2 2.5 T = 105°C 1.
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ATmega48PA/88PA/168PA Electrical Characteristics 33.2.3 ATmega168PA DC Characteristics – Current Consumption Table 33-5. DC characteristics - TA = -40°C to 85/105°C, VCC = 1.8V to 5.5V (unless otherwise noted) Typ.(2) Max. Units T = 85°C 0.2 0.5 mA T = 105°C 0.3 0.6 T = 85°C 1.2 2.5 T = 105°C 1.8 2.75 T = 85°C 4.2 9.0 T = 105°C 6.7 10 T = 85°C 0.03 0.15 T = 105°C 0.06 0.2 T = 85°C 0.2 0.7 T = 105°C 0.4 0.8 T = 85°C 0.9 2.7 T = 105°C 1.7 3 32 kHz TOSC enabled, VCC = 1.
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ATmega48PA/88PA/168PA Electrical Characteristics Figure 33-1. Maximum Frequency vs. VCC 20MHz 10MHz Safe Operating Area 4MHz 1.8V 33.4 2.7V 4.5V 5.5V Clock Characteristics Related Links 13.6 Calibrated Internal RC Oscillator 13.12.1 OSCCAL 33.4.1 Calibrated Internal RC Oscillator Accuracy Table 33-6. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory 8.0 MHz Calibration 3.0V 25°C ±10% User Fixed frequency within: Calibration 7.3 - 8.
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ATmega48PA/88PA/168PA Electrical Characteristics 33.4.3 External Clock Drive Table 33-7. External Clock Drive Symbol Parameter VCC= 1.8 - 5.5V VCC= 2.7 - 5.5V VCC= 4.5 - 5.5V Units Min. Max. Min. Max. Min. Max. 1/tCLCL Oscillator Frequency 0 4 0 10 0 20 MHz tCLCL Clock Period 250 - 100 - 50 - ns tCHCX High Time 100 - 40 - 20 - ns tCLCX Low Time 100 - 40 - 20 - ns tCLCH Rise Time - 2.0 - 1.6 - 0.5 μs tCHCL Fall Time - 2.0 - 1.6 - 0.
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ATmega48PA/88PA/168PA Electrical Characteristics Table 33-9. BODLEVEL Fuse Coding(1)(2) BODLEVEL [2:0] Fuses Min. VBOT Typ. VBOT Max VBOT Units 111 BOD Disabled 110 1.7 1.8 2.0 V 101 2.5 2.7 2.9 100 4.1 4.3 4.5 011 - 000 Reserved Note: VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test.
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ATmega48PA/88PA/168PA Electrical Characteristics Description Mode Min. 17 SS high to tri-state Slave 18 SS low to SCK Slave Typ Max Units 10 - 2 • tck - - Note: In SPI Programming mode the minimum SCK high/low period is: • 2 • tCLCLCL for fCK < 12 MHz • 3 • tCLCL for fCK > 12 MHz Figure 33-3. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 7 MOSI (Data Output) 8 MSB ... LSB Figure 33-4.
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ATmega48PA/88PA/168PA Electrical Characteristics Table 33-11. Two-Wire Serial Bus Requirements Symbol Parameter Condition Min. Max Units V VIL Input Low-voltage -0.5 0.3 VCC VIH Input High-voltage 0.7 VCC VCC + 0.5 V Vhys(1) Hysteresis of Schmitt Trigger Inputs 0.05 VCC(2) – V VOL(1) Output Low-voltage 0 0.4 V tr(1) Rise Time for both SDA and SCL 20 + 0.1Cb(3)(2) 300 ns tof(1) Output Fall Time from VIHmin to 10 pF < Cb < 400 pF(3) VILmax 20 + 0.
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ATmega48PA/88PA/168PA Electrical Characteristics Symbol Parameter tBUF Condition Bus free time between a STOP fSCL ≤ 100 kHz and START condition fSCL > 100 kHz Min. Max Units 4.7 – μs 1.3 – μs Note: 1. This parameter is characterized and not 100% tested. 2. Required only for fSCL > 100 kHz. 3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency. 5. This requirement applies to all two-wire serial interface operation.
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ATmega48PA/88PA/168PA Electrical Characteristics Symbol Parameter Condition Min. Typ Max Units Gain Error VREF = 4V, VCC = 4V, ADC clock = 200 kHz - 2 - LSB Offset Error VREF = 4V, VCC = 4V, ADC clock = 200 kHz - 2 - LSB Conversion Time Free Running Conversion 13 - 260 μs Clock Frequency 50 - 1000 kHz AVCC(1) Analog Supply Voltage VCC - 0.3 - VCC + 0.3 V VREF Reference Voltage 1.0 - AVCC V VIN Input Voltage GND - VREF V Input Bandwidth - 38.
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ATmega48PA/88PA/168PA Electrical Characteristics Symbol Parameter Min. Max Units tPLWL PAGEL Low to WR Low 67 - ns tBVWL BS1 Valid to WR Low 67 - ns tWLWH WR Pulse Width Low 150 - ns tWLRL WR Low to RDY/BSY Low 0 1 μs tWLRH WR Low to RDY/BSY High(1) 3.2 3.4 ms tWLRH_CE WR Low to RDY/BSY High for Chip Erase(2) 9.8 10.
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ATmega48PA/88PA/168PA Electrical Characteristics Note: The timing requirements shown in 33.9 Parallel Programming Characteristics (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation Figure 33-8.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) 34. Typical Characteristics (TA = -40°C to 105°C) The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pullups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-Down mode is independent of clock selection.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-2. ATmega48PA: Active Supply Current vs. Frequency (1 MHz - 20 MHz) 11 5.5V 10 9 5.0V 8 4.5V ICC (mA) 7 6 4.0V 5 4 3.3V 3 2.7V 2 1 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 34-3. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.05 105°C 0.045 85°C 0.04 ICC (mA) 0.035 0.03 25°C -40°C 0.025 0.02 0.015 0.01 0.005 1.5 2 2.5 3 3.5 4 4.5 5 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-4. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 105°C 85°C 25°C -40°C 1.2 1.1 1 ICC (mA) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-5. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 5.5 105°C 85°C 25°C -40°C 5 4.5 ICC (mA) 4 3.5 3 2.5 2 1.5 1 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Idle Supply Current Figure 34-6. ATmega48PA: Idle Supply Current vs. Low Frequency (0.1 MHz - 1.0 MHz) ICC (mA) 0.16 0.14 5.5V 0.12 5.0V 0.1 4.5V 0.08 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 34-7. ATmega48PA: Idle Supply Current vs. Frequency (1 MHz - 20 MHz) 2.6 5.5V 2.4 2.2 5.0V 2 4.5V 1.8 1.6 ICC (mA) 34.1.2 1.4 4.0V 1.2 1 0.8 3.3V 0.6 2.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-8. ATmega48PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.05 105°C 0.045 85°C 0.04 ICC (mA) 0.035 0.03 25°C -40°C 0.025 0.02 0.015 0.01 0.005 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-9. ATmega48PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 0.33 105°C 85°C 25°C -40°C ICC (mA) 0.28 0.23 0.18 0.13 0.08 1.5 2 2.5 3 3.5 4 4.5 5 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-10. ATmega48PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 1.3 105°C 85°C 25°C -40°C 1.2 1.1 1 ICC (mA) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 34.1.3 Supply Current of I/O Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) PRR bit Additional Current consumption compared to Active with external clock (see Figure 34-1 and Figure 34-2) Additional Current consumption compared to Idle with external clock (see Figure 34-6 and Figure 34-7) PRTIM2 2.9% 15.7% PRTIM1 2.1% 11.2% PRTIM0 0.8% 4.2% PRSPI 3.3% 17.6% PRADC 4.2% 22.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-12. ATmega48PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 9 105°C 8.5 8 -40°C 85°C 25°C 7.5 7 ICC (µA) 6.5 6 5.5 5 4.5 4 3.5 3 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-Save Supply Current Figure 34-13. Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32 kHz Crystal Oscillator Running) 2.5 2.25 105°C 2 1.75 Icc [µA] 34.1.5 1.5 85°C 1.25 1 0.75 25°C 0.5 -40°C 0.25 0 1.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) 34.1.6 Standby Supply Current Figure 34-14. ATmega48PA: Standby Supply Current vs. Vcc (Watchdog Timer Disabled) 6MHz_xtal 6MH z _r e s 150 135 120 4MH z _r e s 4MHz_xtal 105 ICC (µA) 90 2MH z _r e s 2MHz_xtal 75 60 1MHz_res 450kHz_res 45 30 15 0.0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pin Pull-Up Figure 34-15. ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 45 40 35 30 IOP (µA) 34.1.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-16. ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 70 60 IOP (µA) 50 40 30 20 25°C 85°C -40°C 105°C 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VOP (V) Figure 34-17. ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 120 105 IOP (µA) 90 75 60 45 30 25°C 85°C 105°C -40°C 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-18. ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 35 30 IRESET (µA) 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 25°C -40°C 105°C 85°C 1.8 VRESET (V) Figure 34-19. ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 52 48 44 40 IRESET (µA) 36 32 28 24 20 16 12 25°C -40°C 85°C 105°C 8 4 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-20. ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 110 100 90 80 IRESET (µA) 70 60 50 40 30 85°C 25°C -40°C 105°C 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V) Pin Driver Strength Figure 34-21. ATmega48PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3V) 1 105°C 85°C 0.9 0.8 25°C 0.7 0.6 VOL (V) 34.1.8 -40°C 0.5 0.4 0.3 0.2 0.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-22. ATmega48PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5V) Figure 34-23. ATmega48PA: I/O Pin Output Voltage vs. Source Current (Vcc = 3V) 3 2.9 2.8 2.7 VOH (V) 2.6 2.5 2.4 -40°C 2.3 2.2 25°C 2.1 2 85°C 105°C 1.9 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-24. ATmega48PA: I/O Pin Output Voltage vs. Source Current (VCC = 5V) 5 4.9 VOH (V) 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 105°C 4.3 0 2 4 8 6 10 12 14 16 18 20 IOH (mA) Pin Threshold and Hysteresis Figure 34-25. ATmega48PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 105°C 85°C -40°C 25°C 2.9 2.6 2.3 Threshold (V) 34.1.9 2 1.7 1.4 1.1 0.8 1.5 2 2.5 3 3.5 4 4.5 5 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-26. ATmega48PA: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’ 105°C -40°C 85°C 25°C 2.4 2.1 Threshold (V) 1.8 1.5 1.2 0.9 0.6 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-27. ATmega48PA: I/O Pin Input Hysteresis vs. VCC 0.6 -40 °C 25°C 85°C 105°C -40°C Input Hysteresis (mV) 0.55 0.5 0.45 25 °C 0.4 85 °C 0.35 0.3 105 °C 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-28. ATmega48PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 105°C 85°C -40°C 25°C 2.45 Threshold (V) 2.2 1.95 1.7 1.45 1.2 -40°C 25°C 85°C 105°C 0.95 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-29. ATmega48PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) -40°C 2.4 105°C 85°C 2.2 25°C Threshold (V) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-30. ATmega48PA: Reset Pin Input Hysteresis vs. VCC 0.65 0.6 -40°C 0.55 Input Hysteresis (mV) 0.5 0.45 25°C 0.4 0.35 0.3 85°C 0.25 0.2 0.15 105°C 85°C 105°C 25°C -40°C 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 34.1.10 BOD Threshold Figure 34-31. ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8V) 1.825 1.82 Rising Vcc 1.815 Threshold (V) 1.81 1.805 1.8 1.795 1.79 Falling Vcc 1.785 1.78 1.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-32. ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) 2.76 2.75 Rising Vcc 2.74 Threshold (V) 2.73 2.72 2.71 2.7 2.69 2.68 Falling Vcc 2.67 2.66 2.65 2.64 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Figure 34-33. ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) 4.34 4.32 Rising Vcc Threshold (V) 4.3 4.28 4.26 Falling Vcc 4.24 4.22 4.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-34. ATmega48PA: Bandgap Voltage vs. VCC 1.1325 1.13 Bandgap Voltage [V] 1.1275 105°C 85°C 1.125 25°C 1.1225 1.12 1.1175 1.115 -40°C 1.1125 1.11 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc [V] 34.1.11 Internal Oscillator Speed Figure 34-35. ATmega48PA: Watchdog Oscillator Frequency vs. Temperature 116 114 FRC (kHz) 112 110 108 2.7V 3.3V 4.0V 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-36. ATmega48PA: Watchdog Oscillator Frequency vs. VCC FRC (kHz) 116 114 -40°C 112 25°C 110 108 85°C 106 105°C 104 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-37. ATmega48PA: Calibrated 8 MHz RC Oscillator Frequency vs. VCC 8.25 8.2 105°C 8.15 85°C 8.1 FRC (MHz) 8.05 8 25°C 7.95 7.9 7.85 7.8 7.75 -40°C 7.7 7.65 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-38. ATmega48PA: Calibrated 8 MHz RC Oscillator Frequency vs. Temperature 4.0V 3.0V 5.5V 8.2 8.15 1.8V 8.1 8.05 FRC (MHz) 8 7.95 7.9 7.85 7.8 7.75 7.7 7.65 -40 -20 -30 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Figure 34-39. ATmega48PA: Calibrated 8 MHz RC Oscillator Frequency vs.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) 34.1.12 Current Consumption of Peripheral Units Figure 34-40. ATmega48PA: ADC Current vs. VCC (AREF = AVCC) -40°C 25°C 85°C 105°C 310 290 270 ICC (µA) 250 230 210 190 170 150 130 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-41. ATmega48PA: Analog Comparator Current vs. VCC 90 -40°C 85 80 25°C 85°C 105°C 75 ICC (µA) 70 65 60 55 50 45 105°C 85°C 25°C 35 -40°C 40 1.5 2 2.5 3 3.5 4 4.5 5 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-42. ATmega48PA: AREF External Reference Current vs. VCC 105°C 85°C 25°C -40°C 150 140 130 120 ICC (µA) 110 100 90 80 70 60 50 40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-43. ATmega48PA: Brownout Detector Current vs. VCC 26 25 105°C 85°C 24 23 25°C -40°C ICC (µA) 22 21 20 19 18 17 16 15 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-44. ATmega48PA: Programming Current vs. VCC 5.5 -40°C 5 25°C 4.5 ICC (mA) 4 3.5 3 85°C 105°C 2.5 2 1.5 1 1.5 2 3 2.5 3.5 4 4.5 5 5.5 VCC (V) 34.1.13 Current Consumption in Reset and Reset Pulsewidth Figure 34-45. ATmega48PA: Reset Supply Current vs. Low Frequency (0.1 MHz - 1.0 MHz) 0.13 5.5V 0.12 0.11 5.0V 0.1 0.09 4.5V ICC (mA) 0.08 4.0V 0.07 0.06 0.05 3.3V 0.04 2.7V 0.03 1.8V 0.02 0.01 0 0 0.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-46. ATmega48PA: Reset Supply Current vs. Frequency (1 MHz - 20 MHz) 2.4 5.5V 2.2 5.0V 2 1.8 4.5V ICC (mA) 1.6 1.4 4.0V 1.2 1 0.8 3.3V 0.6 2.7V 0.4 0.2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 34-47. ATmega48PA: Minimum Reset Pulse Width vs. Vcc © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) 34.2 ATmega88PA: Typical Characteristics 34.2.1 Active Supply Current ATmega88PA: ActiveSupply Supply Current Current vs. Frequency (0.1MHz -1.0MHz) Figure 34-48. ATmega88PA: Active vs.Low Low Frequency (0.1 MHz - 1.0 MHz) 1 0.9 5.5V 0.8 5.0V ICC (mA) 0.7 4.5V 0.6 4.0V 0.5 0.4 3.3V 0.3 2.7V 0.2 1.8V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ATmega88PA: Active Supply Current vs.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) ATmega88PA: ActiveSupply Supply Current Current vs. (Internal RC RC Oscillator, 128kHz) Figure 34-50. ATmega88PA: Active vs.VCC VCC (Internal Oscillator, 128 kHz) 0.14 105°C 0.12 -40°C 25°C ICC (mA) 0.1 85°C 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-51. ATmega88PA: ActiveSupply Supply Current vs. VCC (Internal RC Oscillator, ATmega88PA: Active Current vs.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) ATmega88PA: Active SupplyCurrent Current vs. RCRC Oscillator, 8MHz) Figure 34-52. ATmega88PA: Active Supply vs. VVCC (Internal Oscillator, 8 MHz) CC(Internal 6 105°C 85°C 25°C -40°C 5 ICC (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current ATmega88PA: Idle Supply Current LowFrequency Frequency (0.1MHz Figure 34-53. ATmega88PA: Idle Supply Current vs.vs.Low (0.1 MHz-1.0MHz) - 1.0 MHz) 0.14 5.5V 0.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-54. ATmega88PA: Idle Supply Current vs.vs. Frequency MHz - 20MHz) 20 MHz) ATmega88PA: Idle Supply Current Frequency(1(1MHz 2.5 5.5V 2 ICC (mA) 5.0V 4.5V 1.5 4.0V 1 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) ATmega88PA:Idle Idle Supply Supply Current vs.vs. VCCV(Internal RC Oscillator, 128kHz) Figure 34-55. ATmega88PA: Current RC Oscillator, 128 kHz) CC (Internal 0.05 0.045 105°C 0.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) ATmega88PA: Idle Supply Current VCC (InternalRC RCOscillator, Oscillator, 1MHz) Figure 34-56. ATmega88PA: Idle Supply Current vs.vs. VCC (Internal 1 MHz) 0.4 105°C 0.35 85°C 25°C 0.25 -40°C ICC (mA) 0.3 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega88PA: SupplyCurrent Current vs. vs. VCC Oscillator, 8MHz) Figure 34-57. ATmega88PA: IdleIdle Supply (InternalRC RC Oscillator, 8 MHz) CC (Internal 1.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) PRR bit Typical numbers (µA) VCC = 2V, F = 1 MHz VCC = 3V, F = 4 MHz VCC = 5V, F = 8 MHz PRTIM2 5.2 35.2 149.5 PRTIM1 3.8 25.6 110.0 PRTIM0 1.5 9.8 39.6 PRSPI 5.2 40.0 199.6 PRADC 6.3 48.7 247.0 Table 34-4.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Power-Down Supply Current Figure 34-58. ATmega88PA: Supply Current VCC (Watchdog Disabled) ATmega88PA: Power-Down Power-Down Supply Current vs. Vvs. Timer Timer Disabled) CC (Watchdog 5 105°C ICC (µA) 4 3 2 85°C 1 25°C -40°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-59. ATmega88PA: Power-Down Current (Watchdog Enabled) ATmega88PA: Power-Down Supply Supply Current vs.vs.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) 34.2.5 Power-Save Supply Current Figure 34-60. ATmega88PA: SupplyCurrent Current Disabled and 32 CC (Watchdog ATmega88PA:Power-Save Power-Save Supply vs.vs. VCCV(Watchdog TimerTimer Disabled kHz Crystal Oscillator Running) and 32kHz Crystal Oscillator Running) 6 105°C ICC (µA) 4 85°C 2 25°C -40°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Standby Supply Current Figure 34-61. Standby Supply Current vs.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Pin Pull-Up ATmega88PA:I/O I/OPin Pin Pull-up Pull-up Resistor Current vs. Input Voltage (VCC =(V 1.8V) Figure 34-62. ATmega88PA: Resistor Current vs. Input Voltage CC = 1.8V) 60 50 IOP (µA) 40 30 20 25°C 10 -40°C 0 85°C 105°C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) ATmega88PA:I/O I/OPin Pin Pull-up Pull-up Resistor Current vs. vs. Input Voltage (VCC =(V2.7V) Figure 34-63.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-64. ATmega88PA: ResistorCurrent Current Input Voltage (V5V) ATmega88PA:I/O I/OPin PinPull-up Pull-up Resistor vs.vs. Input Voltage (VCC = CC = 5V) 160 140 120 IOP (µA) 100 80 60 25°C 40 -40°C 85°C 105°C 20 0 0 1 2 3 4 5 6 VOP (V) Figure 34-65. ATmega88PA: ATmega88PA:Reset Reset Pull-up Resistor Current vs. Pin Reset Pin Voltage (VCC = 1.8V) Pull-up Resistor Current vs. Reset Voltage (VCC = 1.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-66. ATmega88PA: ResetPull-up Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) ATmega88PA: Reset Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET (µA) 40 30 20 25°C -40°C 85°C 105°C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 34-67. ATmega88PA: Pull-upResistor Resistor Current vs. Reset Pin Voltage ATmega88PA: Reset Reset Pull-up Current vs.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Pin Driver Strength ATmega88PA: I/O Pin Output Voltage vs. Sink Current (V = 3V) Figure 34-68. ATmega88PA: I/O Pin Output Voltage vs. Sink Current (VCC CC = 3V) 1.2 1 105°C 85°C VOL (V) 0.8 25°C 0.6 -40°C 0.4 0.2 0 0 5 10 15 20 25 IOL (mA) Figure 34-69. ATmega88PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5V) ATmega88PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 0.7 0.6 105°C 85°C 0.5 VOL (V) 34.2.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-70. ATmega88PA: I/O Pin Output vs. Source Current (Vcc(Vcc = 3V) ATmega88PA: I/O Pin Voltage Output Voltage vs. Source Current = 3V) 3.5 VOH (V) 3 2.5 -40°C 25°C 85°C 105°C 2 1.5 0 5 10 15 20 25 IOH (mA) Figure 34-71. ATmega88PA: I/O I/O PinPin Output Current = 5V) = 5V) ATmega88PA: OutputVoltage Voltagevs. vs. Source Source Current (V(V CCCC 5.2 5 VOH (V) 4.8 4.6 -40°C 25°C 4.4 85°C 105°C 4.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Pin Threshold and Hysteresis Figure 34-72. ATmega88PA: InputThreshold Threshold Voltage I/Oread Pin as read ATmega88PA:I/O I/O Pin Pin Input Voltage vs. vs. VCC V (VCC I/O ‘1’) as ‘1’) IH,Pin IH,(V 3.5 105°C 85°C 25°C -40°C 3 Threshold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-73. ATmega88PA: I/OPin PinInput Input Threshold Voltage VCC (VIL , I/O Pinasread ATmega88PA: I/O Threshold Voltage vs. Vvs.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-74. ATmega88PA: I/O Pin Input Hysteresis vs. VCC ATmega88PA: I/O Pin Input Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 -40°C 0.5 25°C 0.4 85°C 0.3 105°C 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega88PA: ResetInput Input Threshold Threshold Voltage vs.vs. VCCVCC (VIH(V , I/O Pin read as ‘1’) Figure 34-75. ATmega88PA: Reset Voltage IH, I/O Pin read as ‘1’) 2.5 Threshold (V) 2 1.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) ATmega88PA: ResetInput InputThreshold Threshold Voltage VCC (VIL(V , I/O, I/O Pin Pin readread as ‘0’) Figure 34-76. ATmega88PA: Reset Voltagevs.vs. VCC as ‘0’) IL 2.5 105°C 85°C 25°C -40°C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-77. Reset PinATmega88PA: Input Hysteresis vs. Reset PinVCC Input Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 -40°C 0.5 25°C 0.4 0.3 85°C 0.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) 34.2.10 BOD Threshold ATmega88PA: Thresholds Temperature (BODLEVEL (BODLEVEL isis1.8V) Figure 34-78. ATmega88PA: BODBOD Thresholds vs.vs.Temperature 1.8V) 1.84 1.83 Rising Vcc Threshold (V) 1.82 1.81 1.8 1.79 1.78 Falling Vcc 1.77 1.76 -60 -40 -20 0 20 40 60 80 100 120 Temperature (°C) ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL 2.7V) Figure 34-79. ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL isis2.7V) 2.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) Figure 34-80. ATmega88PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) 4.5 4.45 4.4 Rising Vcc Threshold (V) 4.35 4.3 4.25 Falling Vcc 4.2 4.15 4.1 4.05 4 -60 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 34-81. ATmega88PA: Calibrated Bandgap Voltage vs. Temperature 1.09 1.8V 2.7V 3.3V 4.0V 4.5V 5.5V 1.085 Bandgap Voltage [V] 1.08 1.075 1.07 1.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-82. ATmega88PA: Bandgap Voltage vs. VCC 1.09 1.085 105°C 85°C Bandgap Voltage [V] 1.08 1.075 25°C 1.07 1.065 1.06 1.055 -40°C 1.05 1.045 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc [V] 34.2.11 Internal Oscillator Speed ATmega88PA: Watchdog Oscillator Frequency vs. Temperature Figure 34-83. ATmega88PA: Watchdog Oscillator Frequency vs. Temperature 116 114 FRC (kHz) 112 110 108 2.7V 3.3V 4.0V 106 104 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) ATmega88PA: Watchdog Oscillator Frequencyvs. vs. VVCC Figure 34-84. ATmega88PA: Watchdog Oscillator Frequency CC 116 114 -40°C FRC (kHz) 112 25°C 110 108 106 85°C 104 105°C 102 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-85. ATmega88PA: Calibrated 8 MHz RCRC Oscillator vs.VVCC ATmega88PA: Calibrated 8MHz OscillatorFrequency Frequency vs. CC 8.5 105°C 85°C FRC (MHz) 8.25 25°C 8 -40°C 7.75 7.5 1.5 2 2.5 3 3.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-86. ATmega88PA: Calibrated 8MHz RCRC Oscillator vs.Temperature Temperature ATmega88PA: Calibrated 8MHz Oscillator Frequency Frequency vs. 8.4 5.5V 4.0V 3.0V 8.3 FRC (MHz) 8.2 1.8V 8.1 8 7.9 7.8 7.7 7.6 -60 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 34-87. ATmega88PA: Calibrated RC Oscillator Oscillator Frequency vs. OSCCAL ATmega88PA: Calibrated 8MHz 8MHz RC Frequency vs.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) 34.2.12 Current Consumption of Peripheral Units ATmega88PA: ADC Current = AV Figure 34-88. ATmega88PA: ADC Current vs. Vvs. (AREF = AV CC (AREF CC V CC)CC) 350 -40°C 300 25°C 85°C 105°C ICC (µA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega88PA: Analog Comparator Current vs. VCC Figure 34-89. ATmega88PA: Analog Comparator Current vs. VCC 90 80 70 ICC (µA) 60 105°C 50 40 30 85°C 25°C -40°C 20 10 0 1.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) ATmega88PA: External Reference Currentvs. vs.VVCC Figure 34-90. ATmega88PA: AREFAREF External Reference Current CC 160 105°C 85°C 25°C -40°C 140 120 ICC (µA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATmega88PA: Brownout Figure 34-91. ATmega88PA: Brownout Detector CurrentDetector vs. VCCCurrent vs. VCC 30 25 ICC (µA) 20 15 105°C 85°C 25°C -40°C 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) ATmega88PA:Current Programming Current vs. VCC Figure 34-92. ATmega88PA: Programming vs. VCC 10 9 8 -40°C ICC (mA) 7 6 5 25°C 4 85°C 3 105°C 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 34.2.13 Current Consumption in Reset and Reset Pulsewidth Figure 34-93. ATmega88PA: Reset vs.Low Low Frequency (0.1 MHz - 1.0 MHz) ATmega88PA: ResetSupply Supply Current Current vs. Frequency (0.1MHz - 1.0MHz) 0.12 5.5V 0.1 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) ATmega88PA: Reset Supply Current vs. Frequency (1MHz - 20MHz) Figure 34-94. ATmega88PA: Reset Supply Current vs. Frequency (1 MHz - 20 MHz) 2.5 5.5V 2 ICC (mA) 5.0V 1.5 4.5V 4.0V 1 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) ATmega88PA: Minimum Reset Pulse widthvs. vs.VVccCC Figure 34-95.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) 34.3 ATmega168PA Typical Characteristics 34.3.1 Active Supply Current Figure 34-96. ATmega168PA: Active Supply Current vs. Low Frequency (0.1 MHz - 1.0 MHz) 1 5.5V ICC (mA) 0.9 0.8 5.0V 0.7 4.5V 0.6 4.0V 0.5 0.4 3.3V 0.3 2.7V 0.2 1.8V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 34-97. ATmega168PA: Active Supply Current vs. Frequency (1 MHz - 20 MHz) 12 5.5V 10 5.0V 4.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-98. ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.14 105°C -40°C 85°C 25°C 0.12 ICC (mA) 0.1 0.08 0.06 0.04 0.02 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-99. ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 1.2 105°C 85°C 25°C -40°C 1.1 1 ICC (mA) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-100. ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 5.5 105°C 85°C 25°C -40°C 5 4.5 ICC (mA) 4 3.5 3 2.5 2 1.5 1 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 34-101. ATmega168PA: Idle Supply Current vs. Low Frequency (0.1 MHz - 1.0 MHz) 0.16 5.5V 0.14 5.0V 0.12 ICC (mA) 34.3.2 0.1 4.5V 0.08 4.0V 3.6V 0.06 2.7V 0.04 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-102. ATmega168PA: Idle Supply Current vs. Frequency (1 MHz - 20 MHz) 12 5.5V 10 5.0V 4.5V ICC (mA) 8 6 4.0V 3.6V 4 2.7V 2 1.8V 0 0 2 4 8 6 10 12 14 16 18 20 Frequency (MHz) Figure 34-103. ATmega168PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) 0.045 105°C 0.04 85°C 0.035 ICC (mA) 0.03 25°C -40°C 0.025 0.02 0.015 0.01 0.005 1.5 2 2.5 3 3.5 4 4.5 5 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-104. ATmega168PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 0.3 105°C 85°C 25°C -40°C 0.27 0.24 ICC (mA) 0.21 0.18 0.15 0.12 0.09 0.06 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-105. ATmega168PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 1.3 105°C 85°C 25°C -40°C 1.1 ICC (mA) 0.9 0.7 0.5 0.3 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 34.3.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) PRR Bit Typical Numbers (µA) VCC = 2V, F = 1 MHz VCC = 3V, F = 4 MHz VCC = 5V, F = 8 MHz PRTIM1 3.50 23.0 55.3 PRTIM0 1.43 9.2 21.4 PRSPI 5.01 38.6 111.4 PRADC 6.34 45.7 123.6 Table 34-6.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Power-Down Supply Current Figure 34-106. ATmega168PA: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) 2.4 105°C 2.1 1.8 ICC (µA) 1.5 1.2 0.9 85°C 0.6 0.3 25°C -40°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-107. ATmega168PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 9 105°C 8 -40°C 85°C 25°C 7 ICC (µA) 34.3.4 6 5 4 3 1.5 2 2.5 3 3.5 4 4.5 5 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) 34.3.5 Power-Save Supply Current Figure 34-108. ATmega168PA: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32 kHz Crystal Oscillator Running) 4 105°C 3.5 ICC (µA) 3 2.5 85°C 2 1.5 -40°C 25°C 1 0.5 1.5 2 3 2.5 3.5 4 4.5 5 5.5 VCC (V) Standby Supply Current Figure 34-109. ATmega168PA: Standby Supply Current vs. Vcc (Watchdog Timer Disabled) 0.15 6 MHz_res 6 MHz_xtal 0.14 0.13 0.12 4 MHz_res 4 MHz_xtal 0.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Pin Pull-Up Figure 34-110. ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 45 40 IOP (µA) 35 30 25 20 15 25°C -40°C 85°C 105°C 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP (V) Figure 34-111. ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 50 IOP (µA) 34.3.7 40 30 25°C 85°C -40°C 105°C 20 10 0 0 0.5 1 1.5 2 2.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-112. ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 140 120 IOP (µA) 100 80 60 40 25°C 85°C -40°C 105°C 20 0 0 1 2 3 4 5 VOP (V) Figure 34-113. ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET (µA) 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET (V) Figure 34-114. ATmega168PA: Reset Pull-up Resistor Current vs.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-115. ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 100 IRESET (µA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V) Pin Driver Strength Figure 34-116. ATmega168PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3V) 1 105°C 85°C 0.9 0.8 0.7 VOL (V) 34.3.8 25°C 0.6 -40°C 0.5 0.4 0.3 0.2 0.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-117. ATmega168PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 0.6 105°C 85°C 0.5 25°C -40°C VOL (V) 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 34-118. ATmega168PA: I/O Pin Output Voltage vs. Source Current (Vcc = 3V) 3.1 2.9 VOH (V) 2.7 2.5 -40°C 2.3 25°C 2.1 85°C 105°C 1.9 1.7 0 5 10 15 20 IOH (mA) © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-119. ATmega168PA: I/O Pin Output Voltage vs. Source Current (VCC = 5V) 5 4.9 VOH (V) 4.8 4.7 4.6 -40°C 4.5 25°C 85°C 105°C 4.4 4.3 0 5 10 15 20 IOH (mA) Pin Threshold and Hysteresis Figure 34-120. ATmega168PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 3 105°C 85°C 25°C -40°C 2.8 2.6 2.4 Threshold (V) 34.3.9 2.2 2 1.8 1.6 1.4 1.2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-121. ATmega168PA: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 105°C 85°C 25°C -40°C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-122. ATmega168PA: I/O Pin Input Hysteresis vs. VCC 85°C 105°C 0.6 -40°C Input Hysteresis (V) 0.55 0.5 25°C 0.45 0.4 0.35 0.3 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-123. ATmega168PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’) 1.5 -40°C 25°C 85°C 105°C 1.4 Threshold (V) 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-124. ATmega168PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’) 2.5 105°C 85°C 25°C -40°C 2.3 2.1 Threshold (V) 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-125. ATmega168PA: Reset Pin Input Hysteresis vs. VCC 0.7 -40°C 0.6 Input Hysteresis (V) 0.5 25°C 0.4 0.3 85°C 0.2 105°C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 34.3.10 BOD Threshold Figure 34-126. ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8V) 1.83 1.82 Rising Vcc Threshold (V) 1.81 1.8 1.79 Falling Vcc 1.78 1.77 1.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-127. ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) 2.76 2.74 Rising Vcc Threshold (V) 2.72 2.7 2.68 Falling Vcc 2.66 2.64 2.62 -40 -20 -30 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature (°C) Figure 34-128. ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) 4.32 Rising Vcc Threshold (V) 4.3 4.28 4.26 4.24 Falling Vcc 4.22 4.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-130. ATmega168PA: Calibrated Bandgap Voltage vs. Temperature 1.136 1.8V 2.7V 3.3V 4.0V 4.5V 1.134 Bandgap Voltage (V) 1.132 1.13 1.128 5.5V 1.126 1.124 1.122 1.12 1.118 1.116 -50 -10 -30 10 30 50 70 90 110 Temperature (°C) 34.3.11 Internal Oscillator Speed Figure 34-131. ATmega168PA: Watchdog Oscillator Frequency vs. Temperature 122 120 FRC (kHz) 118 116 114 2.7V 3.3V 4.0V 4.5V 5.5V 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-132. ATmega168PA: Watchdog Oscillator Frequency vs. VCC 122 120 -40°C FRC (kHz) 118 25°C 116 114 112 85°C 110 105°C 108 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-133. ATmega168PA: Calibrated 8 MHz RC Oscillator Frequency vs. VCC 8.5 8.4 105°C 85°C 8.3 FRC (MHz) 8.2 8.1 25°C 8 7.9 7.8 -40°C 7.7 7.6 7.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-134.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-135. ATmega168PA: Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value 14 105°C 85°C 25°C -40°C 12 FRC (MHz) 10 8 6 4 2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 34.3.12 Current Consumption of Peripheral Units Figure 34-136. ATmega168PA: ADC Current vs. VCC (AREF = AVCC) 325 -40°C 25°C 85°C 105°C 300 275 ICC (µA) 250 225 200 175 150 125 100 1.5 2 2.5 3 3.5 4 4.5 5 5.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-137. ATmega168PA: Analog Comparator Current vs. VCC 90 -40°C 105°C 25°C 85°C 80 ICC (µA) 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-138. ATmega168PA: AREF External Reference Current vs. VCC 180 25°C 85°C 105°C -40°C 160 ICC (µA) 140 120 100 80 60 40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-139. ATmega168PA: Brownout Detector Current vs. VCC 28 26 105°C 85°C ICC (µA) 24 25°C -40°C 22 20 18 16 14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-140. ATmega168PA: Programming Current vs. VCC 9 -40°C 25°C 8 7 105°C 85°C ICC (mA) 6 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) 34.3.13 Current Consumption in Reset and Reset Pulsewidth Figure 34-141. ATmega168PA: Reset Supply Current vs. Low Frequency (0.1 MHz - 1.0 MHz) 0.12 5.5V 0.1 ICC (mA) 0.08 4.5V 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 34-142. ATmega168PA: Reset Supply Current vs. Frequency (1 MHz - 20 MHz) 2.4 2.1 5.5V 1.8 5.0V 4.5V ICC (mA) 1.5 1.2 4.0V 0.9 3.6V 0.6 2.
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ATmega48PA/88PA/168PA Typical Characteristics (TA = -40°C to 105°C) Figure 34-143. ATmega168PA: Minimum Reset Pulse Width vs. Vcc 1800 1600 Pulsewidth (ns) 1400 1200 1000 800 600 105°C 85°C 25°C -40°C 400 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Register Summary 35. Register Summary Offset Name Bit Pos.
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ATmega48PA/88PA/168PA Register Summary Offset Name Bit Pos. 0x54 MCUSR 7:0 0x55 MCUCR 7:0 0x56 Reserved 0x57 SPMCSR 7:0 0x57 SPMCSR 7:0 7:0 WDRF BODS BODSE PUD SPMIE RWWSB SIGRD RWWSRE BLBSET SPMIE RWWSB SIGRD RWWSRE BLBSET SP7 SP6 SP5 SP4 SP3 I T H S V WDIE WDP[3] WDCE WDE BORF EXTRF PORF IVSEL IVCE PGWRT PGERS SPMEN PGWRT PGERS SPMEN SP2 SP1 SP0 SP10 SP9 SP8 N Z C 0x58 ...
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ATmega48PA/88PA/168PA Register Summary Offset 0x84 0x86 0x88 0x8A Name Bit Pos. TCNT1L and 7:0 TCNT1[7:0] TCNT1H 15:8 TCNT1[15:8] 7:0 ICR1[7:0] ICR1L and ICR1H 15:8 ICR1[15:8] OCR1AL and 7:0 OCR1A[7:0] OCR1AH 15:8 OCR1A[15:8] OCR1BL and 7:0 OCR1B[7:0] OCR1BH 15:8 OCR1B[15:8] 0x8C ...
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ATmega48PA/88PA/168PA Register Summary 4. 5. on registers containing such Status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses.
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ATmega48PA/88PA/168PA Instruction Set Summary 36.
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ATmega48PA/88PA/168PA Instruction Set Summary BRANCH INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 Indirect Call to (Z) PC ← Z None 3 Direct Subroutine Call PC ← k None 4 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 ICALL CALL(1) k CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd - Rr Z, N,V,C,H 1 CPC Rd,Rr C
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ATmega48PA/88PA/168PA Instruction Set Summary BIT AND BIT-TEST INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C¬Rd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry R
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ATmega48PA/88PA/168PA Instruction Set Summary DATA TRANSFER INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks LD Rd, - X Load Indirect and Pre-Decrement X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Increment Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Decrement Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z)
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ATmega48PA/88PA/168PA Instruction Set Summary MCU CONTROL INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Packaging Information 37. Packaging Information 37.1 32-pin 32A Note: Note: For the most current package drawings, see the Microchip Packaging Specification located at http:// www.microchip.com/packaging PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0°~7° L A1 A2 A COMMON DIMENSIONS (Unit of measure = mm) SYMBOL Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.
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ATmega48PA/88PA/168PA Packaging Information 37.2 32-pin 32M1-A Note: Note: For the most current package drawings, see the Microchip Packaging Specification located at http:// www.microchip.com/packaging D D1 1 2 3 0 Pin 1 ID E1 SIDE VIEW E TOP VIEW A2 A3 A1 A K 0.08 C P D2 SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 1 2 3 P Pin #1 Notch (0.20 R) A3 E2 K e b COMMON DIMENSIONS (Unit of Measure = mm) L BOTTOM VIEW 0.20 REF b 0.18 0.23 0.30 D 4.
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ATmega48PA/88PA/168PA Packaging Information 37.3 32-pin 32CC1 Note: For the most current package drawings, see the Microchip Packaging Specification located at http:// www.microchip.com/packaging 1 2 3 4 5 6 0.08 A B Pin#1 ID C D SIDEVIEW D E F b1 A1 E A A2 TOP VIEW E1 e 1 2 3 4 5 32-Øb 6 F D1 COMMON DIMENSIONS (Unit of Measure = mm) E D SYMBOL MIN A A1 A2 b b1 D D1 E E1 e – 0.12 C B A A1 BALL CORNER e BOTTOM VIEW Note1: Dimension “b” is measured at the maximum ball dia.
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ATmega48PA/88PA/168PA Packaging Information For the most current package drawings, see the Microchip Packaging Specification located at http:// www.microchip.com/packaging D C 1 2 Pin 1 ID 3 E SIDEVIEW A1 TOP VIEW A y D2 K 1 0.45 2 R0.20 3 E2 b L e 0.4 Ref (4x) BOTTOM VIEW i nal #1 ID is a Laser -m a r ked Feat ur e . Note: The ter m COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN A A1 b C D D2 E E2 e L y K 0.80 0.00 0.17 3.95 2.35 3.95 2.35 0.35 0.00 0.20 NOM MAX NOTE 0.90 1.
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ATmega48PA/88PA/168PA Packaging Information D PIN 1 E1 A SEATING PLANE L B2 B1 A1 B (4 PLACES) 0º ~ 15º REF e E C COMMON DIMENSIONS (Unit of Measure = mm) Note: NOM MAX – 4.5724 A1 0.508 – – D 34.544 – 34.798 E 7.620 – 8.255 E1 7.112 – 7.493 B 0.381 – 0.533 B1 1.143 – 1.397 B2 0.762 – 1.143 L 3.175 – 3.429 C 0.203 – 0.356 eB – – 10.160 A 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.
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ATmega48PA/88PA/168PA Errata 38. Errata 38.1 Errata ATmega48PA The revision letter in this section refers to the revision of the ATmega48PA device. 38.1.1 Rev. D 1– Analog MUX can be turned off when setting ACME bit If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1' (ADMUX[3:0]=1xxx), all MUXes are turned off until the ACME bit is cleared. Fix/Workaround: Clear the MUX3 bit before setting the ACME bit.
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ATmega48PA/88PA/168PA Errata Increased AC offset on low input voltages Analog comparator may have an offset greater than 40 mV on low input voltages (Vin < 0.5V) when VCC > 3.6V. Fix/Workaround: Avoid using low input voltages to the analog comparator when VCC is greater than 3.6V 38.2 Errata ATmega88PA The revision letter in this section refers to the revision of the ATmega88PA device. 38.2.1 Rev.
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ATmega48PA/88PA/168PA Errata Fix/Workaround: There is no fix for this problem. 3– Increased AC offset on low input voltages Analog comparator may have an offset greater than 40 mV on low input voltages (Vin < 0.5V) when VCC > 3.6V. Fix/Workaround: Avoid using low input voltages to the analog comparator when VCC is greater than 3.6V 38.3 Errata ATmega168PA The revision letter in this section refers to the revision of the ATmega168PA device. 38.3.1 Rev.
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ATmega48PA/88PA/168PA Errata 2 – TWI data setup time can be too short When running the device as a TWI slave with a system clock above 2 MHz, the data setup time for the first bit after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line. Fix/Workaround: Insert a delay between setting TWDR and TWCR. 38.3.5 Rev. A to D Not sampled. © 2018 Microchip Technology Inc.
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ATmega48PA/88PA/168PA Datasheet Revision History 39. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 39.1 Revision A – 4/2018 Section Changes Full data sheet • • • Change of document style Microchip DS40002011A replaces Atmel-42734B Added bit numbering in registers where this was missing 13.
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ATmega48PA/88PA/168PA The Microchip Web Site Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as a means to make files and information easily available to customers.
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ATmega48PA/88PA/168PA Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
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ATmega48PA/88PA/168PA Legal Notice Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications.
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ATmega48PA/88PA/168PA Quality Management System Certified by DNV ISO/TS 16949 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California ® ® and India. The Company’s quality system processes and procedures are for its PIC MCUs and dsPIC ® DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products.
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Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.