Datasheet

14.12.1 Sleep Mode Control Register

Name: SMCR

Offset: 0x53

Reset: 0x00

Property: When addressing as I/O Register: address offset is 0x33

The Sleep Mode Control register contains control bits for power management.

When addressing I/O registers as data space using LD and ST instructions, the provided offset must be

used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an

I/O address offset within 0x00 - 0x3F.

Bit 7 6 5 4 3 2 1 0

SM[2:0] SE

Access

R/W R/W R/W R/W

Reset 0 0 0 0

Bits 3:1 – SM[2:0] Sleep Mode Select

The SM[2:0] bits select between the five available sleep modes.

Table 14-2. Sleep Mode Select

SM[2:0] Sleep Mode

000 Idle

001 ADC Noise Reduction

010 Power-down

011 Power-save

100 Reserved

101 Reserved

110 Standby

(1)

111 Extended Standby

(1)

Note:

1. Standby mode is only recommended for use with external crystals or resonators.

Bit 0 – SE Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose,

it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP

instruction and to clear it immediately after waking up.

ATmega48PA/88PA/168PA

Power Management and Sleep Modes

Datasheet Complete

DS40002011A-page 74