Datasheet

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to
ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the
next can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is
kept in Reset during the changes.
The system clock prescaler can be used to implement run-time changes of the internal clock frequency
while still ensuring stable operation.
Related Links
13.11 System Clock Prescaler
13.9 Timer/Counter Oscillator
The device uses the same crystal oscillator for low-frequency oscillator and Timer/Counter oscillator. See
Low Frequency Crystal Oscillator for details on the oscillator and crystal requirements.
On this device, the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) are shared with XTAL1 and
XTAL2. When using the Timer/Counter oscillator, the system clock needs to be four times the oscillator
frequency. Due to this and the pin sharing, the Timer/Counter oscillator can only be used when the
calibrated internal RC oscillator is selected as system clock source.
Applying an external clock source to TOSC1 can be done if the Enable External Clock Input bit in the
Asynchronous Status Register (ASSR.EXCLK) is written to '1'. See the description of the Asynchronous
Operation of Timer/Counter2 for further description on selecting external clock as input instead of a
32.768 kHz watch crystal.
Related Links
13.5 Low-Frequency Crystal Oscillator
22.11.5 OCR2B
22.11.8 ASSR
13.10 Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT fuse has to
be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system.
The clock also will be output during Reset, and the normal operation of I/O pin will be overridden when
the fuse is programmed. Any clock source, including the internal RC oscillator, can be selected when the
clock is output on CLKO. If the system clock prescaler is used, it is the divided system clock that is
output.
13.11 System Clock Prescaler
The device has a system clock prescaler and the system clock can be divided by configuring the Clock
Prescale Register (CLKPR). This feature can be used to decrease the system clock frequency and the
power consumption when the requirement for processing power is low. This can be used with all clock
source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk
I/O
,
clk
ADC
, clk
CPU
, and clk
FLASH
are divided by a factor as shown in the CLKPR description.
When switching between prescaler settings, the system clock prescaler ensures that no glitches occur in
the clock system. It also ensures that no intermediate frequency is higher than neither the clock
frequency corresponding to the previous setting nor the clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may
ATmega48PA/88PA/168PA
System Clock and Clock Options
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 63