Datasheet

1. Wait until EEPE becomes zero.

2. Wait until SPMEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a '1' to the EEMPE bit while writing a zero to EEPE in EECR.

6. Within four clock cycles after setting EEMPE, write a '1' to EEPE.

The EEPROM cannot be programmed during a CPU write to the Flash memory. The software must check

that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if

the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being

updated by the CPU, step 2 can be omitted.

CAUTION

An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master

Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another

EEPROM access, the EEAR or EEDR register will be modified, causing the interrupted

EEPROM access to fail. It is recommended to have the global interrupt flag cleared during all

the steps to avoid these problems.

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user

software can poll this bit and wait for a zero before writing the next byte. When EEPE has been

set, the CPU is halted for two cycles before the next instruction is executed.

Bit 0 – EERE EEPROM Read Enable

The EEPROM read enable signal EERE is the read strobe to the EEPROM. When the correct address is

set up in the EEAR register, the EERE bit must be written to a '1' to trigger the EEPROM read. The

EEPROM read access takes one instruction, and the requested data is available immediately. When the

EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it

is neither possible to read the EEPROM, nor to change the EEAR register.

The calibrated oscillator is used to time the EEPROM accesses. See the following table for typical

programming times for EEPROM access from the CPU.

Table 12-2. EEPROM Programming Time

Symbol Number of Calibrated RC Oscillator Cycles Typ. Programming Time

EEPROM write (from CPU) 26,368 3.3ms

The following code examples show one assembly and one C function for writing to the EEPROM. The

examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts

will occur during execution of these functions. The examples also assume that no Flash Boot Loader is

present in the software. If such code is present, the EEPROM write function must also wait for any

ongoing SPM command to finish.

Assembly Code Example

(1)

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

ATmega48PA/88PA/168PA

AVR Memories

Datasheet Complete

DS40002011A-page 48