Datasheet

The algorithm for reading the Fuse Low byte (FLB) is similar to the one described above for reading the
Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN
bits in SPMCSR (SPMCSR.BLBSET and SPMCSR.SPMEN). When an LPM instruction is executed within
three cycles after the SPMCSR.BLBSET and SPMCSR.SPMEN are set, the value of the Fuse Low byte
(FLB) will be loaded in the destination register as shown below. Refer to the table Fuse Low Byte in Fuse
Bits of Memory Programming chapter for a detailed description and mapping of the Fuse Low byte.
Bit 7 6 5 4 3 2 1 0
Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0
Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an LPM instruction
is executed within three cycles after the SPMCSR.BLBSET and SPMCSR.SPMEN are set, the value of
the Fuse High byte (FHB) will be loaded in the destination register as shown below. Refer to the table
Fuse High Byte for this device in Fuse Bits of Memory Programming chapter for detailed description and
mapping of the Fuse High byte.
Bit 7 6 5 4 3 2 1 0
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0
When reading the Extended Fuse byte (EFB), load 0x0002 in the Z-pointer. When an LPM instruction is
executed within three cycles after the SPMCSR.BLBSET and SPMCSR.SPMEN are set, the value of the
Extended Fuse byte (EFB) will be loaded in the destination register as shown below. Refer to the table
Extended Fuse Byte for ATmega88PA/ATmega168PA in Fuse Bits of Memory Programming chapter for
detailed description and mapping of the Extended Fuse byte.
Bit 7 6 5 4 3 2 1 0
Rd
EFB7 EFB6 EFB5 EFB4 EFB3 EFB2 EFB1 EFB0
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
Related Links
32.2 Fuse Bits
32.2.1 Latching of Fuses
30.2.3 Preventing Flash Corruption
During periods of low V
CC
, the Flash program can be corrupted because the supply voltage is too low for
the CPU and the Flash to operate properly. These issues are the same as for board level systems using
the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular
write sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can
execute instructions incorrectly, if the supply voltage for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one is sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be
done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the
detection level. If not, an external low V
CC
reset protection circuit can be used. If a Reset occurs
while a write operation is in progress, the write operation will be completed provided that the power
supply voltage is sufficient.
2. Keep the AVR core in Power-down sleep mode during periods of low V
CC
. This will prevent the
CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR
register and thus the Flash from unintentional writes.
ATmega48PA/88PA/168PA
Self-Programming the Flash
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 340