Datasheet

27.3.2 Digital Input Disable Register 1
Name: DIDR1
Offset: 0x7F
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
AIN1D AIN0D
Access
R R R R R R R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 0, 1 – AIND AIN Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding
PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the
AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce
power consumption in the digital input buffer.
ATmega48PA/88PA/168PA
Analog Comparator (AC)
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Datasheet Complete
DS40002011A-page 313